[PATCH v4 0/3] arm: dts: altera: add Draeger M48 CPU Module

[PATCH v4 0/3] arm: dts: altera: add Draeger M48 CPU Module

[Petko Manolov]

Adding the device trees for “Dräger M48 on NXP i.MX6 (Q) and Intel/Altera
SoCFPGA Cyclone V” board variant.  It has both (the SoC and FPGA) on the same
carrier and they are cross-monitoring each other.

This is the SoCFPGA devicetree part.

Changes in v4:

  - fix commit messages formatting;
  - remove stray comment from the .dts;
  - remove undocumented "bank-name" property;

Changes in v3:

  - add Draeger AG in devicetree/bindings/vendor-prefixes.yaml
  - separate binding changes from the actual devicetree patch
  - remove "earlyprintk" from the boot arguments

Petko Manolov (3):
  dt-bindings: vendor-prefixes: add Draeger AG
  dt-bindings: arm: altera: add Draeger M48 Module
  arm: dts: altera: add Draeger M48 CPU Module

 .../devicetree/bindings/arm/altera.yaml       |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/arm/boot/dts/intel/socfpga/Makefile      |   1 +
 .../socfpga/socfpga_cyclone5_draeger_m48.dts  | 123 ++++++++++++++++++
 4 files changed, 127 insertions(+)
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts

-- 
2.47.3

[PATCH v4 1/3] dt-bindings: vendor-prefixes: add Draeger AG

[Petko Manolov]

Add a vendor prefix for Draegar AG, which is Draegerwerk AG & Co. KGaA

Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ba2002969373..276d62b848d5 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -467,6 +467,8 @@ patternProperties:
     description: DPTechnics
   "^dptel,.*":
     description: Guangdong Dapu Telecom Co., Ltd.
+  "^draeger,.*":
+    description: Draegerwerk AG & Co. KGaA
   "^dragino,.*":
     description: Dragino Technology Co., Limited
   "^dream,.*":
-- 
2.47.3

[PATCH v4 2/3] dt-bindings: arm: altera: add Draeger M48 Module

[Petko Manolov]

Add DT compatible string for Draeger's M48 CPU Module, an i.MX6
based board.

Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
---
 Documentation/devicetree/bindings/arm/altera.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 3030cf46fe74..8ed1ba733510 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -47,6 +47,7 @@ properties:
           - enum:
               - altr,socfpga-cyclone5-socdk
               - denx,mcvevk
+              - draeger,M48
               - ebv,socrates
               - macnica,sodia
               - novtech,chameleon96
-- 
2.47.3

[PATCH v4 3/3] arm: dts: altera: add Draeger M48 CPU Module

[Petko Manolov]

Draeger M48 is a CPU module built around the NXP i.MX6q.

Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
---
 arch/arm/boot/dts/intel/socfpga/Makefile      |   1 +
 .../socfpga/socfpga_cyclone5_draeger_m48.dts  | 123 ++++++++++++++++++
 2 files changed, 124 insertions(+)
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts

diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile
index 8df0976da01c..cdcea11abdfa 100644
--- a/arch/arm/boot/dts/intel/socfpga/Makefile
+++ b/arch/arm/boot/dts/intel/socfpga/Makefile
@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
 	socfpga_arria10_mercury_aa1_st1_emmc.dtb \
 	socfpga_arria10_mercury_aa1_st1_qspi.dtb \
 	socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \
+	socfpga_cyclone5_draeger_m48.dtb \
 	socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \
 	socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \
 	socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
new file mode 100644
index 000000000000..838708acb31b
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2020 Draeger and Licensors, info@draeger.com
+ */
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "Draeger M48 Cyclone V SoC";
+	compatible = "draeger,M48", "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+
+	aliases {
+		/* this allow the ethaddr uboot environmnet variable contents
+		 * to be added to the gmac0 device tree blob.
+		 */
+		ethernet0 = &gmac0;
+	};
+
+	soc {
+		gpio3: gpio@ff202000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff202000 0x20>;
+
+			portd: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <2>;
+				reg = <0>;
+			};
+		};
+
+		gpio4: gpio@ff202020 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff202020 0x20>;
+
+			porte: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <2>;
+				reg = <0>;
+			};
+		};
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	rxc-skew-ps = <1860>;
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	rxdv-skew-ps = <0>;
+	txc-skew-ps = <900>;
+	txd0-skew-ps = <0>;
+	txd1-skew-ps = <0>;
+	txd2-skew-ps = <0>;
+	txd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	eeprom_mac: eeprom@50 {
+		compatible = "atmel,24c08";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
+&mmc0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+
+	flash: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		reg = <0>;
+
+		/* chip select */
+		spi-max-frequency = <100000000>;
+		m25p,fast-read;
+		cdns,read-delay = <4>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+	};
+};
-- 
2.47.3

Re: [PATCH v4 2/3] dt-bindings: arm: altera: add Draeger M48 Module

[Krzysztof Kozlowski]

On Fri, Sep 11, 2026 at 06:07:53PM +0300, Petko Manolov wrote:
> Add DT compatible string for Draeger's M48 CPU Module, an i.MX6
> based board.

Sashiko comment is valid.

Best regards,
Krzysztof

Re: [PATCH v4 2/3] dt-bindings: arm: altera: add Draeger M48 Module

[Petko Manolov]

On 26-09-13 11:18:16, Krzysztof Kozlowski wrote:
> On Fri, Sep 11, 2026 at 06:07:53PM +0300, Petko Manolov wrote:
> > Add DT compatible string for Draeger's M48 CPU Module, an i.MX6
> > based board.
> 
> Sashiko comment is valid.

Sashiko doesn't know that this is indeed an i.MX6q board with the Altera FPGA as
a separate module, that is secondary to the NXP SoC.

What do you want me to put in the commit message so that everyone is happy?


		Petko

Re: [PATCH v4 2/3] dt-bindings: arm: altera: add Draeger M48 Module

[Krzysztof Kozlowski]

On 13/09/2026 15:32, Petko Manolov wrote:
> On 26-09-13 11:18:16, Krzysztof Kozlowski wrote:
>> On Fri, Sep 11, 2026 at 06:07:53PM +0300, Petko Manolov wrote:
>>> Add DT compatible string for Draeger's M48 CPU Module, an i.MX6
>>> based board.
>>
>> Sashiko comment is valid.
> 
> Sashiko doesn't know that this is indeed an i.MX6q board with the Altera FPGA as
> a separate module, that is secondary to the NXP SoC.
> 
> What do you want me to put in the commit message so that everyone is happy?

Your commit msgs for bindings and DTS should explain the hardware and
with the current explanation this is just so incomplete that basically
wrong. i.mx6 is completely different vendor. Altera FPGA does not make
it Altera SoCFPGA, these are two different things. If Linux runs on
iMX6, then what are you describing here? DTS which never is going to be
loaded because there is no SocFPGA?

Best regards,
Krzysztof

Re: [PATCH v4 2/3] dt-bindings: arm: altera: add Draeger M48 Module

[Petko Manolov]

On 26-09-13 16:20:54, Krzysztof Kozlowski wrote:
> On 13/09/2026 15:32, Petko Manolov wrote:
> > On 26-09-13 11:18:16, Krzysztof Kozlowski wrote:
> >> On Fri, Sep 11, 2026 at 06:07:53PM +0300, Petko Manolov wrote:
> >>> Add DT compatible string for Draeger's M48 CPU Module, an i.MX6
> >>> based board.
> >>
> >> Sashiko comment is valid.
> > 
> > Sashiko doesn't know that this is indeed an i.MX6q board with the Altera FPGA as
> > a separate module, that is secondary to the NXP SoC.
> > 
> > What do you want me to put in the commit message so that everyone is happy?
> 
> Your commit msgs for bindings and DTS should explain the hardware and with the
> current explanation this is just so incomplete that basically wrong. i.mx6 is

Incomplete - yes, but who cares.  The only consumer is Draeger and they know
better than anyone else what the board looks like and what it is for.

Wrong - how?

> completely different vendor. Altera FPGA does not make it Altera SoCFPGA,
> these are two different things. If Linux runs on iMX6, then what are you
> describing here? DTS which never is going to be loaded because there is no
> SocFPGA?

I'm no Draeger employee, but i've been told that both the i.MX6 and the FPGA are
running Linux (both chips are on the same physical board) and are monitoring
each other's health.  Apart from doing whatever whatever their primary task is.
Whichever fails, the other guy takes over on the fly. This is a medical device
so full redundancy is a must.

So, again and in order to save everyone's time, please elaborate (preferably
with an existing example) whatever it is that you expect to see in the cover
letter and the commit messages.


		Petko