From: Zhi Wang <zhiw@nvidia.com>
To: <dakr@kernel.org>, <acourbot@nvidia.com>
Cc: <alex@shazbot.org>, <jgg@nvidia.com>, <yishaih@nvidia.com>,
<skolothumtho@nvidia.com>, <kevin.tian@intel.com>,
<airlied@gmail.com>, <simona@ffwll.ch>, <ojeda@kernel.org>,
<alex.gaynor@gmail.com>, <boqun.feng@gmail.com>,
<gary@garyguo.net>, <bjorn3_gh@protonmail.com>,
<lossin@kernel.org>, <a.hindborg@kernel.org>,
<aliceryhl@google.com>, <tmgross@umich.edu>,
<jhubbard@nvidia.com>, <ecourtney@nvidia.com>, <cjia@nvidia.com>,
<smitra@nvidia.com>, <kjaju@nvidia.com>, <alkumar@nvidia.com>,
<ankita@nvidia.com>, <aniketa@nvidia.com>, <kwankhede@nvidia.com>,
<targupta@nvidia.com>, <nova-gpu@lists.linux.dev>,
<linux-kernel@vger.kernel.org>, <zhiwang@kernel.org>,
Zhi Wang <zhiw@nvidia.com>
Subject: [PATCH v2 18/32] gpu: nova-core: vgpu: add VRAM slot allocator
Date: Mon, 14 Sep 2026 10:48:53 +0300 [thread overview]
Message-ID: <20260914074907.1399629-19-zhiw@nvidia.com> (raw)
In-Reply-To: <20260914074907.1399629-1-zhiw@nvidia.com>
From: Alok Kumar <alkumar@nvidia.com>
A vGPU type specifies the guest VRAM and GSP plugin management-heap
sizes for each instance. Allocating these regions independently fragments
VRAM and does not preserve a stable layout for the vGPU type.
Add a standalone slot allocator that reserves one exact VRAM range and
tracks assignments in a bitmap. Validate the vGPU type's layout and reject
an allocation request whose layout differs from the active pool.
Lay out all guest VRAM slots first and all management-heap slots
second, pairing them by bitmap index. Require the guest VRAM stride and
pool base to satisfy the required VMMU-segment alignment.
Signed-off-by: Alok Kumar <alkumar@nvidia.com>
Co-developed-by: Zhi Wang <zhiw@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/vgpu.rs | 1 +
drivers/gpu/nova-core/vgpu/vram.rs | 146 +++++++++++++++++++++++++++++
2 files changed, 147 insertions(+)
create mode 100644 drivers/gpu/nova-core/vgpu/vram.rs
diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs
index 348af9ea3fc2..6a876f8539f0 100644
--- a/drivers/gpu/nova-core/vgpu.rs
+++ b/drivers/gpu/nova-core/vgpu.rs
@@ -21,6 +21,7 @@
};
mod hal;
+mod vram;
/// vGPU state detected during GPU construction.
#[derive(Debug, Clone, Copy)]
diff --git a/drivers/gpu/nova-core/vgpu/vram.rs b/drivers/gpu/nova-core/vgpu/vram.rs
new file mode 100644
index 000000000000..2dc751b28ae3
--- /dev/null
+++ b/drivers/gpu/nova-core/vgpu/vram.rs
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+//! VRAM slot allocation for vGPU instances.
+
+#![expect(dead_code)]
+
+use kernel::{
+ bitmap::BitmapVec,
+ prelude::*,
+ sync::Arc, //
+};
+
+use crate::mm::{
+ vram::{
+ VramBlock,
+ VramRegion, //
+ },
+ GpuMm, //
+};
+
+const VRAM_SLOT_MIN_ALIGN: u64 = 4096;
+
+#[derive(Clone, Copy, PartialEq)]
+pub(super) struct VgpuVramLayout {
+ pub(super) type_id: u32,
+ pub(super) max_slots: u32,
+ pub(super) fb_size: u64,
+ pub(super) heap_size: u64,
+ pub(super) fb_align: u64,
+}
+
+impl VgpuVramLayout {
+ fn validated(mut self) -> Result<Self> {
+ if self.max_slots == 0 || self.fb_size == 0 || self.heap_size == 0 {
+ return Err(EINVAL);
+ }
+ self.fb_align = core::cmp::max(self.fb_align, VRAM_SLOT_MIN_ALIGN);
+ if !self.fb_align.is_power_of_two() {
+ return Err(EINVAL);
+ }
+ if self.fb_size & (self.fb_align - 1) != 0
+ || self.heap_size & (VRAM_SLOT_MIN_ALIGN - 1) != 0
+ {
+ return Err(EINVAL);
+ }
+ Ok(self)
+ }
+}
+
+/// Dropping a slot does not release its reservation.
+#[must_use]
+pub(super) struct VgpuVramSlot {
+ index: usize,
+ pub(super) fbmem: VramRegion,
+ pub(super) mgmt_heap: VramRegion,
+}
+
+impl VgpuVramSlot {
+ /// Return this slot's index in the allocation pool for its vGPU type.
+ pub(super) const fn index(&self) -> usize {
+ self.index
+ }
+}
+
+pub(super) struct VgpuVramSlotAllocator {
+ backing: Arc<VramBlock>,
+ layout: VgpuVramLayout,
+ fb_region_size: u64,
+ used: BitmapVec,
+}
+
+impl VgpuVramSlotAllocator {
+ pub(super) fn new(mm: &GpuMm<'_>, layout: VgpuVramLayout) -> Result<Self> {
+ let layout = layout.validated()?;
+ let max_slots = u64::from(layout.max_slots);
+ // Keep guest VRAM slots contiguous so each starts at `fb_align`;
+ // interleaving page-aligned heaps could misalign later slots.
+ let fb_region_size = layout.fb_size.checked_mul(max_slots).ok_or(EINVAL)?;
+ let heap_region_size = layout.heap_size.checked_mul(max_slots).ok_or(EINVAL)?;
+ let pool_size = fb_region_size.checked_add(heap_region_size).ok_or(EINVAL)?;
+
+ let used = BitmapVec::new(
+ usize::try_from(layout.max_slots).map_err(|_| EINVAL)?,
+ GFP_KERNEL,
+ )?;
+ let backing = mm.alloc_vram_range(0..pool_size, VRAM_SLOT_MIN_ALIGN)?;
+ if !backing.address().is_multiple_of(layout.fb_align) {
+ return Err(EINVAL);
+ }
+
+ Ok(Self {
+ backing,
+ layout,
+ fb_region_size,
+ used,
+ })
+ }
+
+ pub(super) fn matches_layout(&self, layout: VgpuVramLayout) -> Result<bool> {
+ Ok(self.layout == layout.validated()?)
+ }
+
+ pub(super) fn alloc(&mut self, layout: VgpuVramLayout) -> Result<VgpuVramSlot> {
+ if !self.matches_layout(layout)? {
+ return Err(EBUSY);
+ }
+
+ let bitmap_index = self.used.next_zero_bit(0).ok_or(ENOSPC)?;
+ let slot = u64::try_from(bitmap_index).map_err(|_| EINVAL)?;
+ let fb_offset = self.layout.fb_size.checked_mul(slot).ok_or(EINVAL)?;
+ let fb_end = fb_offset.checked_add(self.layout.fb_size).ok_or(EINVAL)?;
+ let heap_offset = self
+ .fb_region_size
+ .checked_add(self.layout.heap_size.checked_mul(slot).ok_or(EINVAL)?)
+ .ok_or(EINVAL)?;
+ let heap_end = heap_offset
+ .checked_add(self.layout.heap_size)
+ .ok_or(EINVAL)?;
+ let fbmem = self.backing.region(fb_offset..fb_end)?;
+ let mgmt_heap = self.backing.region(heap_offset..heap_end)?;
+
+ self.used.set_bit(bitmap_index);
+
+ Ok(VgpuVramSlot {
+ index: bitmap_index,
+ fbmem,
+ mgmt_heap,
+ })
+ }
+
+ /// Drop a slot's region views and return its reservation to this pool.
+ ///
+ /// The slot must come from this allocator. All accesses and mappings of its
+ /// regions must end before releasing it.
+ pub(super) fn release(&mut self, slot: VgpuVramSlot) {
+ let index = slot.index;
+ debug_assert_eq!(self.used.next_bit(index), Some(index));
+ drop(slot);
+ self.used.clear_bit(index);
+ }
+
+ pub(super) fn is_empty(&self) -> bool {
+ self.used.last_bit().is_none()
+ }
+}
next prev parent reply other threads:[~2026-09-14 7:52 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
2026-09-14 7:48 ` [PATCH v2 01/32] gpu: nova-core: gsp: pass boot context through setup helpers Zhi Wang
2026-09-14 7:48 ` [PATCH v2 02/32] gpu: nova-core: gsp: decouple boot context from VgpuManager Zhi Wang
2026-09-14 7:48 ` [PATCH v2 03/32] gpu: nova-core: vgpu: detect boot state independently Zhi Wang
2026-09-14 7:48 ` [PATCH v2 04/32] gpu: nova-core: gpu: add a channel ID pool for vGPU Zhi Wang
2026-09-14 7:48 ` [PATCH v2 05/32] gpu: nova-core: gsp: expose the VMMU segment size Zhi Wang
2026-09-14 7:48 ` [PATCH v2 06/32] gpu: nova-core: gsp: decode the FIFO engine table Zhi Wang
2026-09-14 7:48 ` [PATCH v2 07/32] gpu: nova-core: vgpu: initialize runtime parameters after GSP boot Zhi Wang
2026-09-14 7:48 ` [PATCH v2 08/32] gpu: nova-core: vgpu: reserve the 48-VM WPR2 heap Zhi Wang
2026-09-14 7:48 ` [PATCH v2 09/32] gpu: nova-core: mm: borrow BarUser for temporary BAR1 access Zhi Wang
2026-09-14 7:48 ` [PATCH v2 10/32] gpu: nova-core: mm: add VramBlock Zhi Wang
2026-09-14 7:48 ` [PATCH v2 11/32] gpu: nova-core: mm: add VramRegion Zhi Wang
2026-09-14 7:48 ` [PATCH v2 12/32] gpu: nova-core: mm: add BarMapping Zhi Wang
2026-09-14 7:48 ` [PATCH v2 13/32] gpu: nova-core: gsp: dispatch RM RPC messages during GMC receive Zhi Wang
2026-09-14 7:48 ` [PATCH v2 14/32] gpu: nova-core: gsp: add synchronous GMC transactions Zhi Wang
2026-09-14 7:48 ` [PATCH v2 15/32] gpu: nova-core: gsp: add status-only " Zhi Wang
2026-09-14 7:48 ` [PATCH v2 16/32] gpu: nova-core: gsp: wait for GMC completion events Zhi Wang
2026-09-14 7:48 ` [PATCH v2 17/32] gpu: nova-core: vgpu: add r000 plugin bindings Zhi Wang
2026-09-14 7:48 ` Zhi Wang [this message]
2026-09-14 7:48 ` [PATCH v2 19/32] gpu: nova-core: gsp: factor out NVKV payload conversion Zhi Wang
2026-09-14 7:48 ` [PATCH v2 20/32] gpu: nova-core: vgpu: query VF assignments and properties Zhi Wang
2026-09-14 7:48 ` [PATCH v2 21/32] gpu: nova-core: vgpu: add instance create/destroy Zhi Wang
2026-09-14 7:48 ` [PATCH v2 22/32] gpu: nova-core: vgpu: encode vGPU boot requests Zhi Wang
2026-09-14 7:48 ` [PATCH v2 23/32] gpu: nova-core: vgpu: add GSP plugin communication buffers Zhi Wang
2026-09-14 7:48 ` [PATCH v2 24/32] gpu: nova-core: vgpu: add instance boot and shutdown Zhi Wang
2026-09-14 7:49 ` [PATCH v2 25/32] gpu: nova-core: vgpu: initialize GSP plugin RPC buffers Zhi Wang
2026-09-14 7:49 ` [PATCH v2 26/32] gpu: nova-core: vgpu: add GSP plugin RPC transactions Zhi Wang
2026-09-14 7:49 ` [PATCH v2 27/32] gpu: nova-core: vgpu: negotiate the GSP plugin RPC version Zhi Wang
2026-09-14 7:49 ` [PATCH v2 28/32] gpu: nova-core: vgpu: send GSP plugin configuration parameters Zhi Wang
2026-09-14 7:49 ` [PATCH v2 29/32] gpu: nova-core: vgpu: update the GSP plugin BME state Zhi Wang
2026-09-14 7:49 ` [PATCH v2 30/32] gpu: nova-core: vgpu: scrub guest VRAM with CeUtils Zhi Wang
2026-09-14 7:49 ` [PATCH v2 31/32] gpu: nova-core: add build ID headers to debugfs log buffer dumps Zhi Wang
2026-09-14 7:49 ` [PATCH v2 32/32] gpu: nova-core: vgpu: export plugin log buffers via debugfs Zhi Wang
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