[PATCH v2 06/32] gpu: nova-core: gsp: decode the FIFO engine table

[Zhi Wang <zhiw@nvidia.com>]

From: Alok Kumar <alkumar@nvidia.com>

GSP_INIT reports the FIFO engine table needed to build the engine bitmap
used during vGPU instance creation.

Decode the engine count, GMC IDs and flags, and expose host-driven
engines in GetGspStaticInfoReply. Preserve firmware FIFO order and
duplicate IDs while filtering on the host-driven flag.

Cc: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Alok Kumar <alkumar@nvidia.com>
Co-developed-by: Zhi Wang <zhiw@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
 drivers/gpu/nova-core/gsp/commands.rs    | 47 +++++++++++++++++++++++-
 drivers/gpu/nova-core/gsp/fw/commands.rs | 34 ++++++++++++++++-
 2 files changed, 79 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs
index afc32c2a230e..3820320dcb34 100644
--- a/drivers/gpu/nova-core/gsp/commands.rs
+++ b/drivers/gpu/nova-core/gsp/commands.rs
@@ -26,7 +26,8 @@
                 GspInitResponse,
                 GspInitResponseSchema,
                 RegKey,
-                VfInfo, //
+                VfInfo,
+                MAX_FIFO_ENGINES, //
             },
             GMCAPI_CMD_GSP_INIT,
             GMCAPI_CMD_GSP_SUSPEND, //
@@ -44,6 +45,28 @@
     vgpu::VgpuState, //
 };
 
+/// Bit mask for `NVGMC_SC_ENGINE_FLAGS_IS_HOST_DRIVEN`.
+const ENGINE_FLAGS_IS_HOST_DRIVEN: u32 = 1 << 0;
+
+/// Host-driven GMC engine IDs in hardware FIFO order, including any repeated IDs.
+///
+/// # Invariants
+///
+/// `count` is at most [`MAX_FIFO_ENGINES`]. The first `count` slots are the retained engine IDs.
+#[derive(Copy, Clone)]
+pub(crate) struct FifoEngineList {
+    gmc_ids: [u32; MAX_FIFO_ENGINES],
+    count: usize,
+}
+
+impl FifoEngineList {
+    #[expect(dead_code)]
+    pub(crate) fn gmc_ids(&self) -> &[u32] {
+        // PANIC: The type invariant bounds `count` by the array capacity.
+        &self.gmc_ids[..self.count]
+    }
+}
+
 /// The static GPU configuration, as decoded from the `GSP_INIT` reply.
 pub(crate) struct GetGspStaticInfoReply {
     gpu_name: [u8; 64],
@@ -56,6 +79,8 @@ pub(crate) struct GetGspStaticInfoReply {
     /// VMMU segment size in bytes, or zero if GSP-RM omitted it.
     #[expect(dead_code)]
     pub(crate) vmmu_segment_size: u64,
+    #[expect(dead_code)]
+    pub(crate) fifo_engine_list: FifoEngineList,
 }
 
 /// Error type for [`GetGspStaticInfoReply::gpu_name`].
@@ -274,12 +299,32 @@ fn decode_gsp_info(words: &[u64]) -> Result<GetGspStaticInfoReply> {
         usable_fb_regions.push(region, GFP_KERNEL)?;
     }
 
+    // INVARIANT: The list starts empty and appends at most one ID per supported input slot.
+    let mut fifo_engine_list = FifoEngineList {
+        gmc_ids: [0; MAX_FIFO_ENGINES],
+        count: 0,
+    };
+    for (&gmc_id, &flags) in decoded
+        .fifo_engine_gmc_ids()
+        .iter()
+        .zip(decoded.fifo_engine_flags())
+        .take(decoded.fifo_engine_count())
+    {
+        if flags & ENGINE_FLAGS_IS_HOST_DRIVEN != 0 {
+            // PANIC: At most one slot is filled per input, and the input has at most
+            // MAX_FIFO_ENGINES entries, so the next retained ID always fits.
+            fifo_engine_list.gmc_ids[fifo_engine_list.count] = gmc_id;
+            fifo_engine_list.count += 1;
+        }
+    }
+
     Ok(GetGspStaticInfoReply {
         gpu_name,
         bar1_pde_base: decoded.bar1_pde_base(),
         usable_fb_regions,
         total_fb_end: decoded.total_fb_end().ok_or(EINVAL)?,
         vmmu_segment_size: decoded.vmmu_segment_size(),
+        fifo_engine_list,
     })
 }
 
diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-core/gsp/fw/commands.rs
index c2e199688b79..706ecfa63c01 100644
--- a/drivers/gpu/nova-core/gsp/fw/commands.rs
+++ b/drivers/gpu/nova-core/gsp/fw/commands.rs
@@ -12,7 +12,10 @@
     transmute::AsBytes, //
 };
 
-use crate::gpu::Chipset;
+use crate::{
+    gpu::Chipset,
+    num, //
+};
 
 use crate::gsp::nvkv::{
     nvkv_decode,
@@ -22,6 +25,7 @@
     DecoderValue,
     Encodable,
     Encoder,
+    Indexed,
     Key,
     KeyId,
     Required, //
@@ -286,6 +290,8 @@ pub(crate) fn new(
 
 // Decode:
 
+pub(in crate::gsp) const MAX_FIFO_ENGINES: usize = 64;
+
 // Should decode with UnknownKeyPolicy::Ignore.
 nvkv_decode! {
     /// Schema for the `GSP_INIT` response.
@@ -298,6 +304,9 @@ pub(crate) struct GspInitResponseSchema => GspInitResponse {
         fb_regions: Accumulated<FbRegionSchema>,
         bar1_pde_base: Required<u64, { Self::BAR1_PDE_BASE_KEY }>,
         vmmu_segment_size: Key<u64, { Self::VMMU_SEGMENT_SIZE_KEY }>,
+        fifo_engine_count: Key<u32, { Self::FIFO_ENGINE_COUNT_KEY }>,
+        fifo_engine_gmc_ids: Indexed<u32, MAX_FIFO_ENGINES, { Self::FIFO_ENGINE_GMC_ID_KEY }>,
+        fifo_engine_flags: Indexed<u32, MAX_FIFO_ENGINES, { Self::FIFO_ENGINE_FLAGS_KEY }>,
     }
 }
 
@@ -306,6 +315,9 @@ impl GspInitResponseSchema {
     const GPU_NAME_STRING_KEY: KeyId = 0x2000;
     const BAR1_PDE_BASE_KEY: KeyId = 0x1020;
     const VMMU_SEGMENT_SIZE_KEY: KeyId = 0x1050;
+    const FIFO_ENGINE_COUNT_KEY: KeyId = 0x0500;
+    const FIFO_ENGINE_GMC_ID_KEY: KeyId = 0x0501;
+    const FIFO_ENGINE_FLAGS_KEY: KeyId = 0x0502;
 }
 
 /// Payload of the `GSP_INIT` response.
@@ -315,6 +327,9 @@ pub(crate) struct GspInitResponse {
     fb_regions: KVVec<FbRegion>,
     bar1_pde_base: u64,
     vmmu_segment_size: u64,
+    fifo_engine_count: u32,
+    fifo_engine_gmc_ids: [u32; MAX_FIFO_ENGINES],
+    fifo_engine_flags: [u32; MAX_FIFO_ENGINES],
 }
 
 impl GspInitResponse {
@@ -372,6 +387,23 @@ pub(crate) fn total_fb_end(&self) -> Option<u64> {
     pub(in crate::gsp) const fn vmmu_segment_size(&self) -> u64 {
         self.vmmu_segment_size
     }
+
+    /// Returns the FIFO engine count, limited to the supported table capacity.
+    ///
+    /// An omitted count is zero. Indexed entries outside the capacity are rejected during decode.
+    pub(in crate::gsp) fn fifo_engine_count(&self) -> usize {
+        num::u32_as_usize(self.fifo_engine_count).min(MAX_FIFO_ENGINES)
+    }
+
+    /// Returns GMC engine IDs by hardware FIFO order; omitted slots contain zero.
+    pub(in crate::gsp) fn fifo_engine_gmc_ids(&self) -> &[u32; MAX_FIFO_ENGINES] {
+        &self.fifo_engine_gmc_ids
+    }
+
+    /// Returns per-engine flags by hardware FIFO order; omitted slots contain zero.
+    pub(in crate::gsp) fn fifo_engine_flags(&self) -> &[u32; MAX_FIFO_ENGINES] {
+        &self.fifo_engine_flags
+    }
 }
 
 nvkv_decode! {