From: Qiang Yu <qiang.yu@oss.qualcomm.com>
To: "Manivannan Sadhasivam" <mani@kernel.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Vinod Koul" <vkoul@kernel.org>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>
Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
Qiang Yu <qiang.yu@oss.qualcomm.com>
Subject: [PATCH 0/4] PCI: qcom: Align PHY init sequence with HPG
Date: Tue, 15 Sep 2026 23:04:20 -0700 [thread overview]
Message-ID: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> (raw)
HPG requires the controller/PHY GDSCs to be powered up and all
clocks enabled, then the controller's reset and the PHY's reset
toggled together as one group, with PARF_DEVICE_TYPE set right
after. This series adds the callbacks needed on both sides to
realize that sequence: a phy_reset() call the controller makes as
part of its own reset, and matching phy_ops::init/phy_ops::reset on
the PHY side.
Patches 1-2 move phy_init()/phy_exit() into the RC and EP
controllers' own init/deinit paths, add a phy_reset() call grouped
with each controller's own reset, and move the PARF_DEVICE_TYPE
write to right after that reset group.
Patches 3-4 update the two PHY drivers these controllers can use
(phy-qcom-qmp-pcie[-multiphy].c) to implement phy_ops::init/reset,
matching phy_ops::power_on to what's left once
phy_ops::init/phy_ops::reset are pulled out.
phy_init()/phy_reset() are no-ops against a phy_ops without
phy_ops::init/phy_ops::reset, so patches 1-2 don't change behavior
on any platform by themselves; patches 3-4 are what actually change
the sequence for the platforms using those two PHY drivers. Other
PHY drivers this series doesn't touch (phy-qcom-qmp-pcie-msm8996.c,
phy-qcom-uniphy-pcie-28lp.c, phy-qcom-pcie2.c) are either unaffected
(no phy_ops::init/phy_ops::reset) or only see their
phy_init()/phy_exit() call site moved without a sequence change.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
---
Qiang Yu (4):
PCI: qcom: Move PHY init and add PHY reset call to align with HPG
PCI: qcom-ep: Move PHY init and drive PHY reset to align with HPG
phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on
phy: qcom-qmp-pcie: Split phy_ops into init/exit/reset/power_on
drivers/pci/controller/dwc/pcie-qcom-ep.c | 26 +--
drivers/pci/controller/dwc/pcie-qcom.c | 165 ++++++++++++++-----
drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c | 94 ++++-------
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 184 ++++++++++------------
4 files changed, 257 insertions(+), 212 deletions(-)
---
base-commit: e6e35979777d646fe3c7c94dca7dd32fb25d45f4
change-id: 20260915-align_pcie_init_sequence_0916-571190abea56
Best regards,
--
Qiang Yu <qiang.yu@oss.qualcomm.com>
next reply other threads:[~2026-09-16 6:04 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-16 6:04 Qiang Yu [this message]
2026-09-16 6:04 ` [PATCH 1/4] PCI: qcom: Move PHY init and add PHY reset call to align " Qiang Yu
2026-09-16 6:04 ` [PATCH 2/4] PCI: qcom-ep: Move PHY init and drive PHY reset " Qiang Yu
2026-09-16 6:04 ` [PATCH 3/4] phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on Qiang Yu
2026-09-16 6:04 ` [PATCH 4/4] phy: qcom-qmp-pcie: " Qiang Yu
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