From: Qiang Yu <qiang.yu@oss.qualcomm.com>
To: "Manivannan Sadhasivam" <mani@kernel.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Vinod Koul" <vkoul@kernel.org>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>
Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
Qiang Yu <qiang.yu@oss.qualcomm.com>
Subject: [PATCH 3/4] phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on
Date: Tue, 15 Sep 2026 23:04:23 -0700 [thread overview]
Message-ID: <20260915-align_pcie_init_sequence_0916-v1-3-0b2195836f30@oss.qualcomm.com> (raw)
In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com>
Per HPG, the controller now calls phy_init() from
qcom_pcie_host_init() and phy_reset() from inside its own core reset
assert/deassert. Making that actually happen here needs phy_ops::init
and phy_ops::reset implemented, and phy_ops::power_on adjusted to
match. Split the combined phy_ops::power_on/power_off into
phy_ops::init/exit/reset/power_on to do that.
phy_ops::init enables power domains, regulators, and all PHY clocks
(pipe clock first). phy_ops::reset does the no-CSR reset assert/
delay/deassert/delay. phy_ops::power_on is left with just the PCS
status poll. phy_ops::exit mirrors phy_ops::init in reverse;
phy_ops::power_off is dropped since nothing remains for it to do.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c | 94 +++++++++--------------
1 file changed, 35 insertions(+), 59 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c
index e93cba4369fb..aa7130efca45 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c
@@ -280,20 +280,18 @@ static int qmp_pcie_init(struct phy *phy)
goto err_pd_power_off;
}
- ret = reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets);
- if (ret) {
- dev_err(qmp->dev, "no-csr reset assert failed: %d\n", ret);
+ ret = clk_bulk_prepare_enable(qmp->cfg->num_pipe_clks, qmp->pipe_clks);
+ if (ret)
goto err_disable_regulators;
- }
-
- usleep_range(200, 300);
ret = clk_bulk_prepare_enable(qmp->cfg->num_clks, qmp->clks);
if (ret)
- goto err_disable_regulators;
+ goto err_disable_pipe_clks;
return 0;
+err_disable_pipe_clks:
+ clk_bulk_disable_unprepare(qmp->cfg->num_pipe_clks, qmp->pipe_clks);
err_disable_regulators:
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
err_pd_power_off:
@@ -310,31 +308,47 @@ static int qmp_pcie_exit(struct phy *phy)
reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets);
clk_bulk_disable_unprepare(qmp->cfg->num_clks, qmp->clks);
+ clk_bulk_disable_unprepare(qmp->cfg->num_pipe_clks, qmp->pipe_clks);
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
qmp_pcie_pd_power_off(qmp);
return 0;
}
-static int qmp_pcie_power_on(struct phy *phy)
+static int qmp_pcie_reset(struct phy *phy)
{
struct qmp_pcie *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
- const struct qmp_pcie_offsets *offs = cfg->offsets;
- void __iomem *status;
- unsigned int val;
- int i, ret;
+ int ret;
- ret = clk_bulk_prepare_enable(qmp->cfg->num_pipe_clks, qmp->pipe_clks);
- if (ret)
+ ret = reset_control_bulk_assert(cfg->num_nocsr_resets, qmp->nocsr_resets);
+ if (ret) {
+ dev_err(qmp->dev, "no-csr reset assert failed: %d\n", ret);
return ret;
+ }
- ret = reset_control_bulk_deassert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets);
+ udelay(5);
+
+ ret = reset_control_bulk_deassert(cfg->num_nocsr_resets, qmp->nocsr_resets);
if (ret) {
dev_err(qmp->dev, "no-csr reset deassert failed: %d\n", ret);
- goto err_disable_pipe_clk;
+ return ret;
}
+ udelay(5);
+
+ return 0;
+}
+
+static int qmp_pcie_power_on(struct phy *phy)
+{
+ struct qmp_pcie *qmp = phy_get_drvdata(phy);
+ const struct qmp_phy_cfg *cfg = qmp->cfg;
+ const struct qmp_pcie_offsets *offs = cfg->offsets;
+ void __iomem *status;
+ unsigned int val;
+ int i, ret;
+
for (i = 0; i < cfg->num_regs; i++) {
status = qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_STATUS];
ret = readl_poll_timeout(status, val, !(val & cfg->phy_status), 200,
@@ -342,56 +356,18 @@ static int qmp_pcie_power_on(struct phy *phy)
if (ret) {
dev_err(qmp->dev, "PHY power on timed-out (%s): %d\n",
cfg->reg_names[i], ret);
- goto err_disable_pipe_clk;
+ return ret;
}
}
return 0;
-
-err_disable_pipe_clk:
- clk_bulk_disable_unprepare(qmp->cfg->num_pipe_clks, qmp->pipe_clks);
-
- return ret;
-}
-
-static int qmp_pcie_power_off(struct phy *phy)
-{
- struct qmp_pcie *qmp = phy_get_drvdata(phy);
-
- clk_bulk_disable_unprepare(qmp->cfg->num_pipe_clks, qmp->pipe_clks);
-
- return 0;
-}
-
-static int qmp_pcie_enable(struct phy *phy)
-{
- int ret;
-
- ret = qmp_pcie_init(phy);
- if (ret)
- return ret;
-
- ret = qmp_pcie_power_on(phy);
- if (ret)
- qmp_pcie_exit(phy);
-
- return ret;
-}
-
-static int qmp_pcie_disable(struct phy *phy)
-{
- int ret;
-
- ret = qmp_pcie_power_off(phy);
- if (ret)
- return ret;
-
- return qmp_pcie_exit(phy);
}
static const struct phy_ops qmp_pcie_phy_ops = {
- .power_on = qmp_pcie_enable,
- .power_off = qmp_pcie_disable,
+ .init = qmp_pcie_init,
+ .exit = qmp_pcie_exit,
+ .power_on = qmp_pcie_power_on,
+ .reset = qmp_pcie_reset,
.owner = THIS_MODULE,
};
--
2.34.1
next prev parent reply other threads:[~2026-09-16 6:04 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-16 6:04 [PATCH 0/4] PCI: qcom: Align PHY init sequence with HPG Qiang Yu
2026-09-16 6:04 ` [PATCH 1/4] PCI: qcom: Move PHY init and add PHY reset call to align " Qiang Yu
2026-09-16 6:04 ` [PATCH 2/4] PCI: qcom-ep: Move PHY init and drive PHY reset " Qiang Yu
2026-09-16 6:04 ` Qiang Yu [this message]
2026-09-16 6:04 ` [PATCH 4/4] phy: qcom-qmp-pcie: Split phy_ops into init/exit/reset/power_on Qiang Yu
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