[PATCH 0/9] Add support for MIPS P8700

[PATCH 0/9] Add support for MIPS P8700

[Aleksa Paunovic via B4 Relay]

The MIPS P8700 is a multi-core RISC-V microprocessor system, supporting
both single-cluster and multi-cluster configurations. [1]
This series adds full description of the platform,
including the Boston FPGA board configured with a P8700 bitfile.

The P8700 cores support the RV64GCZba_Zbb (G = IMAFD) Standard ISA,
with a caveat: the A extension is only partially supported, and all ZAAMO
extension instructions are emulated on the SBI level. The device tree
intentionally does not reflect this fact.

GlobalFoundries has acquired MIPS [2] and the vendor prefix
for all MIPS RISC-V hardware has been updated to reflect that fact.

All my series so far have used the dts the current one was based on,
with mostly cosmetic changes. Nevertheless, I tested this series
both on QEMU and a Boston board configured with a single P8700 CPU,
after applying the necessary U-Boot and OpenSBI changes
to match the 'compatible' strings. We are planning to upstream these
as well.

Links:
[1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf
[2] https://gf.com/news-and-events/news/globalfoundries-completes-acquisition-of-mips/

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
Aleksa Paunovic (9):
      dt-bindings: vendor-prefixes: Add GlobalFoundries, Inc.
      dt-bindings: riscv: cpus: add gf,mips-p8700
      dt-bindings: riscv: Add MIPS Boston board compatible
      dt-bindings: interrupt-controller: Add MIPS P8700 APLIC
      dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI
      dt-bindings: timer: Add MIPS P8700 ACLINT MTIMER
      dt-bindings: interrupt-controller: thead,c900-aclint-sswi: Add MIPS P8700 gf compatible
      riscv: dts: gf: Initial support for the P8700 Boston board
      riscv: defconfig: Enable GF SoCs

 .../bindings/interrupt-controller/riscv,aplic.yaml |   1 +
 .../thead,c900-aclint-mswi.yaml                    |  34 +++
 .../thead,c900-aclint-sswi.yaml                    |   3 +
 Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
 Documentation/devicetree/bindings/riscv/gf.yaml    |  27 +++
 .../bindings/timer/thead,c900-aclint-mtimer.yaml   |  43 +++-
 .../devicetree/bindings/vendor-prefixes.yaml       |   4 +-
 arch/riscv/Kconfig.socs                            |   6 +
 arch/riscv/boot/dts/Makefile                       |   1 +
 arch/riscv/boot/dts/gf/Makefile                    |   2 +
 arch/riscv/boot/dts/gf/p8700-boston.dts            | 135 ++++++++++++
 arch/riscv/boot/dts/gf/p8700.dtsi                  | 241 +++++++++++++++++++++
 arch/riscv/configs/defconfig                       |   1 +
 13 files changed, 494 insertions(+), 5 deletions(-)
---
base-commit: fd73f4a6659897191fa0d40695fe370925dd3780
change-id: 20260325-p8700-dts-41788f014227

Best regards,
-- 
Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

[PATCH 1/9] dt-bindings: vendor-prefixes: Add GlobalFoundries, Inc.

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

GlobalFoundries acquired MIPS. All MIPS RISC-V
compatibles should be labeled with the 'gf' prefix in the future.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ba2002969373433b1f48118872c46cf7bcfff276..b699935f60b96b3cfbb9c6e8ce802fcbedc52c1b 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -668,6 +668,8 @@ patternProperties:
     description: Genexis BV/AB
   "^geniatech,.*":
     description: Geniatech, Inc.
+  "^gf,.*":
+    description: GlobalFoundries, Inc.
   "^giantec,.*":
     description: Giantec Semiconductor, Inc.
   "^giantplus,.*":
@@ -1104,7 +1106,7 @@ patternProperties:
   "^minix,.*":
     description: MINIX Technology Ltd.
   "^mips,.*":
-    description: MIPS Technology (deprecated, use 'mti' or 'img')
+    description: MIPS Technology (deprecated, use 'mti', 'img', or 'gf')
     deprecated: true
   "^miramems,.*":
     description: MiraMEMS Sensing Technology Co., Ltd.

-- 
2.43.0

[PATCH 2/9] dt-bindings: riscv: cpus: add gf,mips-p8700

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Document the MIPS P8700 compatible.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 0da219ae6769767a9b7f41f179a3559ae7160d69..c7f1cf1db6eef5b25403d53bca7cffd9bc1f2240 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -48,6 +48,7 @@ properties:
               - amd,mbv64
               - andestech,ax45mp
               - canaan,k210
+              - gf,mips-p8700
               - nuclei,ux900
               - sifive,bullet0
               - sifive,e5

-- 
2.43.0

[PATCH 3/9] dt-bindings: riscv: Add MIPS Boston board compatible

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Document the MIPS Boston board compatible with a P8700 bitfile.

Co-developed-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 Documentation/devicetree/bindings/riscv/gf.yaml | 27 +++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/gf.yaml b/Documentation/devicetree/bindings/riscv/gf.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..060910c9b04f482aee6f08f8f72232acbad118bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/gf.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/gf.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GlobalFoundries MIPS SoC-based boards
+
+maintainers:
+  - Djordje Todorovic <djordje.todorovic@htecgroup.com>
+  - Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
+
+description:
+  GlobalFoundries MIPS SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Boston FPGA development board with a MIPS P8700 bitfile
+        items:
+          - const: gf,mips-p8700-boston
+
+additionalProperties: true
+
+...

-- 
2.43.0

[PATCH 4/9] dt-bindings: interrupt-controller: Add MIPS P8700 APLIC

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Document the aplic compatible for the MIPS P8700.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
index 0718071444d29fbfa36283fc9666e8cecd6f77e7..9b986aa1a1c62316a1fd08fe535075111601b80e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
@@ -27,6 +27,7 @@ properties:
   compatible:
     items:
       - enum:
+          - gf,mips-p8700-aplic
           - qemu,aplic
           - spacemit,k3-aplic
       - const: riscv,aplic

-- 
2.43.0

[PATCH 5/9] dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Document the aclint mswi compatible for the MIPS P8700 and
introduce the 'riscv,hart-indexes' property,
used to address the sparse MIPS P8700 harts.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 .../thead,c900-aclint-mswi.yaml                    | 34 ++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
index 62fd220e126e650e3800d8eee2a749fdbbde6108..47c04943eb0c793467aaa5570776605cae0eadfd 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
@@ -17,6 +17,8 @@ properties:
               - sophgo,sg2042-aclint-mswi
               - sophgo,sg2044-aclint-mswi
           - const: thead,c900-aclint-mswi
+      - items:
+          - const: gf,mips-p8700-aclint-mswi
       - items:
           - enum:
               - anlogic,dr1v90-aclint-mswi
@@ -29,6 +31,14 @@ properties:
     minItems: 1
     maxItems: 4095
 
+  riscv,hart-indexes:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 4095
+    description:
+      A list of hart indexes that the MSWI device uses to address each hart
+      that is mentioned in the "interrupts-extended"
+
 additionalProperties: false
 
 required:
@@ -36,6 +46,19 @@ required:
   - reg
   - interrupts-extended
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: gf,mips-p8700-aclint-mswi
+    then:
+      required:
+        - riscv,hart-indexes
+    else:
+      properties:
+        riscv,hart-indexes: false
+
 examples:
   - |
     interrupt-controller@94000000 {
@@ -46,4 +69,15 @@ examples:
                             <&cpu4intc 3>;
       reg = <0x94000000 0x00010000>;
     };
+
+  - |
+    mswi@16150000 {
+      compatible = "gf,mips-p8700-aclint-mswi";
+      reg = <0x16150000 0x4000>;
+      interrupts-extended = <&cpu1intc 3>,
+                            <&cpu2intc 3>,
+                            <&cpu3intc 3>,
+                            <&cpu4intc 3>;
+      riscv,hart-indexes = <0x0 0x1 0x10 0x11>;
+    };
 ...

-- 
2.43.0

[PATCH 6/9] dt-bindings: timer: Add MIPS P8700 ACLINT MTIMER

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Document the MIPS P8700 ACLINT MTIMER.
Extend support for both mtimecmp and mtime registers
within the ACLINT MTIMER, identified via reg-names.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 .../bindings/timer/thead,c900-aclint-mtimer.yaml   | 43 ++++++++++++++++++++--
 1 file changed, 39 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
index cf7c82e980f674afcf59fc726742dc4f49c1a820..35e02da675becb3c8bb187b8e1e623994d52df8c 100644
--- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
+++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
@@ -17,18 +17,20 @@ properties:
               - sophgo,sg2042-aclint-mtimer
               - sophgo,sg2044-aclint-mtimer
           - const: thead,c900-aclint-mtimer
+      - items:
+          - const: gf,mips-p8700-aclint-mtimer
       - items:
           - enum:
               - anlogic,dr1v90-aclint-mtimer
           - const: nuclei,ux900-aclint-mtimer
 
   reg:
-    items:
-      - description: MTIMECMP Registers
+    minItems: 1
+    maxItems: 2
 
   reg-names:
-    items:
-      - const: mtimecmp
+    minItems: 1
+    maxItems: 2
 
   interrupts-extended:
     minItems: 1
@@ -42,6 +44,28 @@ required:
   - reg-names
   - interrupts-extended
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: gf,mips-p8700-aclint-mtimer
+    then:
+      properties:
+        reg:
+          minItems: 2
+        reg-names:
+          items:
+            - const: mtime
+            - const: mtimecmp
+    else:
+      properties:
+        reg:
+          maxItems: 1
+        reg-names:
+          items:
+            - const: mtimecmp
+
 examples:
   - |
     timer@ac000000 {
@@ -53,4 +77,15 @@ examples:
       reg = <0xac000000 0x00010000>;
       reg-names = "mtimecmp";
     };
+
+  - |
+    timer@16108050 {
+      compatible = "gf,mips-p8700-aclint-mtimer";
+      reg = <0x16108050 0x8>, <0x16154000 0x7ff8>;
+      reg-names = "mtime", "mtimecmp";
+      interrupts-extended = <&cpu1intc 7>,
+                            <&cpu2intc 7>,
+                            <&cpu3intc 7>,
+                            <&cpu4intc 7>;
+    };
 ...

-- 
2.43.0

[PATCH 7/9] dt-bindings: interrupt-controller: thead,c900-aclint-sswi: Add MIPS P8700 gf compatible

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Add a new compatible for the MIPS P8700 ACLINT SSWI, with the "gf"
vendor prefix. The original compatible is left as is.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 .../bindings/interrupt-controller/thead,c900-aclint-sswi.yaml          | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
index d02c6886283af790d75357f77a714558f68bb7d1..6c79d7b7058a64bb39141d565f0a6304365991f2 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
@@ -30,6 +30,9 @@ properties:
           - const: thead,c900-aclint-sswi
       - items:
           - const: mips,p8700-aclint-sswi
+      - items:
+          - const: gf,mips-p8700-aclint-sswi
+          - const: mips,p8700-aclint-sswi
       - items:
           - enum:
               - anlogic,dr1v90-aclint-sswi

-- 
2.43.0

[PATCH 8/9] riscv: dts: gf: Initial support for the P8700 Boston board

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Add initial device tree for the MIPS P8700 and the device tree
for the Boston FPGA development board with a MIPS P8700 bitfile.

Add related Makefile and KCONFIG changes.

Co-developed-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 arch/riscv/Kconfig.socs                 |   6 +
 arch/riscv/boot/dts/Makefile            |   1 +
 arch/riscv/boot/dts/gf/Makefile         |   2 +
 arch/riscv/boot/dts/gf/p8700-boston.dts | 135 ++++++++++++++++++
 arch/riscv/boot/dts/gf/p8700.dtsi       | 241 ++++++++++++++++++++++++++++++++
 5 files changed, 385 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 429e0758930687c742c4dd09603e71e90dc096a2..78b0a0076feb14ebdafc4b7f0fa1be3aa416d415 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -18,6 +18,12 @@ config ARCH_ESWIN
 	  This enables support for ESWIN SoC platform hardware,
 	  including the ESWIN EIC7700 SoC.
 
+config ARCH_GF
+	bool "GlobalFoundries SoCs"
+	help
+	  This enables support for GlobalFoundries SoC platform hardware,
+	  including the MIPS P8700.
+
 config ARCH_MICROCHIP_POLARFIRE
 	def_bool ARCH_MICROCHIP
 
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 69d8751fb17c803f0efb8003e111ee24144c222b..5d8d55c4cf9d0b17f2a8744aa17526819e6c277a 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y += andes
 subdir-y += anlogic
 subdir-y += canaan
 subdir-y += eswin
+subdir-y += gf
 subdir-y += microchip
 subdir-y += renesas
 subdir-y += sifive
diff --git a/arch/riscv/boot/dts/gf/Makefile b/arch/riscv/boot/dts/gf/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..180d7cc7f5cf87e48e2219f9ac9882828ca62016
--- /dev/null
+++ b/arch/riscv/boot/dts/gf/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_GF) += p8700-boston.dtb
diff --git a/arch/riscv/boot/dts/gf/p8700-boston.dts b/arch/riscv/boot/dts/gf/p8700-boston.dts
new file mode 100644
index 0000000000000000000000000000000000000000..b829899592aeed5f1cfe3323e755410de07dbdb8
--- /dev/null
+++ b/arch/riscv/boot/dts/gf/p8700-boston.dts
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (C) 2025 MIPS
+ *
+ * Boston FPGA development board with a MIPS P8700 bitfile.
+ */
+
+/dts-v1/;
+
+#include "p8700.dtsi"
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* Clock frequency (in Hz) of the FPGA bitfile */
+#define BITFILE_FREQ	25000000
+
+/ {
+	model = "MIPS P8700 Boston";
+	compatible = "gf,mips-p8700-boston";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	cpus {
+		timebase-frequency = <BITFILE_FREQ>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	pci2: pci@14000000 {
+		compatible = "xlnx,axi-pcie-host-1.00.a";
+		device_type = "pci";
+		reg = <0x14000000 0x2000000>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+
+		interrupt-parent = <&aplic_s0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+
+		ranges = <0x02000000 0 0x16000000
+			  0x16000000 0 0x100000>;
+
+		bus-range = <0x00 0xff>;
+
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pci2_intc 1>,
+				<0 0 0 2 &pci2_intc 2>,
+				<0 0 0 3 &pci2_intc 3>,
+				<0 0 0 4 &pci2_intc 4>;
+
+		pci2_intc: interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+		};
+
+		pci2_root@0,0 {
+			compatible = "pci10ee,7021", "pci-bridge";
+			reg = <0x00000000 0 0 0 0>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			eg20t_bridge@1,0,0 {
+				compatible = "pci8086,8800", "pci-bridge";
+				reg = <0x00010000 0 0 0 0>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+
+				eg20t_mac@2,0,1 {
+					compatible = "pci8086,8802",
+						     "intel,pch-gbe";
+					reg = <0x00020100 0 0 0 0>;
+					phy-reset-gpios = <&eg20t_gpio 6 1>;
+				};
+
+				eg20t_gpio: eg20t_gpio@2,0,2 {
+					compatible = "pci8086,8803",
+						     "intel,eg20t-gpio";
+					reg = <0x00020200 0 0 0 0>;
+
+					gpio-controller;
+					#gpio-cells = <2>;
+				};
+
+				eg20t_i2c@2,12,2 {
+					compatible = "pci8086,8817";
+					reg = <0x00026200 0 0 0 0>;
+
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					rtc@68 {
+						compatible = "st,m41t81s";
+						reg = <0x68>;
+					};
+				};
+			};
+		};
+	};
+
+	uart0: serial@17ffe000 {
+		compatible = "ns16550a";
+		reg = <0x17ffe000 0x1000>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+
+		interrupt-parent = <&aplic_s0>;
+		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+		clock-frequency = <BITFILE_FREQ>;
+	};
+
+	lcd: lcd@17fff000 {
+		compatible = "img,boston-lcd";
+		reg = <0x17fff000 0x8>;
+	};
+
+	flash@18000000 {
+		compatible = "cfi-flash";
+		reg = <0x18000000 0x8000000>;
+		bank-width = <2>;
+	};
+};
diff --git a/arch/riscv/boot/dts/gf/p8700.dtsi b/arch/riscv/boot/dts/gf/p8700.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..ba1854df5201bc4a6ca26868811834a7847dc624
--- /dev/null
+++ b/arch/riscv/boot/dts/gf/p8700.dtsi
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (C) 2025 MIPS
+ */
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "gf,mips-p8700", "riscv";
+			reg = <0x0>;
+			mmu-type = "riscv,sv39";
+			riscv,cbom-block-size = <64>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "zba", "zbb",
+					       "xmipsexectl";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "gf,mips-p8700", "riscv";
+			reg = <0x1>;
+			mmu-type = "riscv,sv39";
+			riscv,cbom-block-size = <64>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "zba", "zbb",
+					       "xmipsexectl";
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu2: cpu@10 {
+			device_type = "cpu";
+			compatible = "gf,mips-p8700", "riscv";
+			reg = <0x10>;
+			mmu-type = "riscv,sv39";
+			riscv,cbom-block-size = <64>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "zba", "zbb",
+					       "xmipsexectl";
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu3: cpu@11 {
+			device_type = "cpu";
+			compatible = "gf,mips-p8700", "riscv";
+			reg = <0x11>;
+			mmu-type = "riscv,sv39";
+			riscv,cbom-block-size = <64>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "zba", "zbb",
+					       "xmipsexectl";
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu4: cpu@20 {
+			device_type = "cpu";
+			compatible = "gf,mips-p8700", "riscv";
+			reg = <0x20>;
+			mmu-type = "riscv,sv39";
+			riscv,cbom-block-size = <64>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "zba", "zbb",
+					       "xmipsexectl";
+
+			cpu4_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu5: cpu@21 {
+			device_type = "cpu";
+			compatible = "gf,mips-p8700", "riscv";
+			reg = <0x21>;
+			mmu-type = "riscv,sv39";
+			riscv,cbom-block-size = <64>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "zba", "zbb",
+					       "xmipsexectl";
+
+			cpu5_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu6: cpu@30 {
+			device_type = "cpu";
+			compatible = "gf,mips-p8700", "riscv";
+			reg = <0x30>;
+			mmu-type = "riscv,sv39";
+			riscv,cbom-block-size = <64>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "zba", "zbb",
+					       "xmipsexectl";
+
+			cpu6_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu7: cpu@31 {
+			device_type = "cpu";
+			compatible = "gf,mips-p8700", "riscv";
+			reg = <0x31>;
+			mmu-type = "riscv,sv39";
+			riscv,cbom-block-size = <64>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "zba", "zbb",
+					       "xmipsexectl";
+
+			cpu7_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		mtimer0: timer@16108050 {
+			compatible = "gf,mips-p8700-aclint-mtimer";
+			reg = <0x16108050 0x8>,
+			      <0x16154000 0x7ff8>;
+			reg-names = "mtime", "mtimecmp";
+			interrupts-extended = <&cpu0_intc 7>, <&cpu1_intc 7>,
+					      <&cpu2_intc 7>, <&cpu3_intc 7>,
+					      <&cpu4_intc 7>, <&cpu5_intc 7>,
+					      <&cpu6_intc 7>, <&cpu7_intc 7>;
+		};
+
+		aplic_m0: interrupt-controller@16140000 {
+			compatible = "gf,mips-p8700-aplic", "riscv,aplic";
+			reg = <0x16140000 0x8000>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
+					      <&cpu2_intc 11>, <&cpu3_intc 11>,
+					      <&cpu4_intc 11>, <&cpu5_intc 11>,
+					      <&cpu6_intc 11>, <&cpu7_intc 11>;
+			riscv,num-sources = <53>;
+			riscv,hart-indexes = <0x00 0x01 0x10 0x11
+					      0x20 0x21 0x30 0x31>;
+			riscv,children = <&aplic_s0>;
+			riscv,delegation = <&aplic_s0 1 53>;
+		};
+
+		mswi0: mswi@16150000 {
+			compatible = "gf,mips-p8700-aclint-mswi";
+			reg = <0x16150000 0x4000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu1_intc 3>,
+					      <&cpu2_intc 3>, <&cpu3_intc 3>,
+					      <&cpu4_intc 3>, <&cpu5_intc 3>,
+					      <&cpu6_intc 3>, <&cpu7_intc 3>;
+			riscv,hart-indexes = <0x00 0x01 0x10 0x11
+					      0x20 0x21 0x30 0x31>;
+		};
+
+		aplic_s0: interrupt-controller@16160000 {
+			compatible = "gf,mips-p8700-aplic", "riscv,aplic";
+			reg = <0x16160000 0x8000>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
+					      <&cpu2_intc 9>, <&cpu3_intc 9>,
+					      <&cpu4_intc 9>, <&cpu5_intc 9>,
+					      <&cpu6_intc 9>, <&cpu7_intc 9>;
+			riscv,num-sources = <53>;
+			riscv,hart-indexes = <0x00 0x01 0x10 0x11
+					      0x20 0x21 0x30 0x31>;
+		};
+
+		sswi0: interrupt-controller@1616c000 {
+			compatible = "gf,mips-p8700-aclint-sswi",
+				     "mips,p8700-aclint-sswi";
+			reg = <0x1616c000 0x4000>;
+			interrupt-controller;
+			#interrupt-cells = <0>;
+			interrupts-extended = <&cpu0_intc 1>, <&cpu1_intc 1>,
+					      <&cpu2_intc 1>, <&cpu3_intc 1>,
+					      <&cpu4_intc 1>, <&cpu5_intc 1>,
+					      <&cpu6_intc 1>, <&cpu7_intc 1>;
+			riscv,hart-indexes = <0x00 0x01 0x10 0x11
+					      0x20 0x21 0x30 0x31>;
+		};
+	};
+};

-- 
2.43.0

[PATCH 9/9] riscv: defconfig: Enable GF SoCs

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Build the MIPS P8700 Boston dtb by default.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 04ae305d5511bb0760247f50d4b69b1e3a00527b..eeac96a0ec878a2d0aa0887d7a7ce71207774a23 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -25,6 +25,7 @@ CONFIG_PROFILING=y
 CONFIG_ARCH_ANDES=y
 CONFIG_ARCH_ANLOGIC=y
 CONFIG_ARCH_ESWIN=y
+CONFIG_ARCH_GF=y
 CONFIG_ARCH_MICROCHIP=y
 CONFIG_ARCH_SIFIVE=y
 CONFIG_ARCH_SOPHGO=y

-- 
2.43.0

Re: [PATCH 1/9] dt-bindings: vendor-prefixes: Add GlobalFoundries, Inc.

[Conor Dooley]

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On Mon, Sep 14, 2026 at 03:55:49PM +0200, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> 
> GlobalFoundries acquired MIPS. All MIPS RISC-V
> compatibles should be labeled with the 'gf' prefix in the future.
> 
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index ba2002969373433b1f48118872c46cf7bcfff276..b699935f60b96b3cfbb9c6e8ce802fcbedc52c1b 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -668,6 +668,8 @@ patternProperties:
>      description: Genexis BV/AB
>    "^geniatech,.*":
>      description: Geniatech, Inc.
> +  "^gf,.*":
> +    description: GlobalFoundries, Inc.
>    "^giantec,.*":
>      description: Giantec Semiconductor, Inc.
>    "^giantplus,.*":
> @@ -1104,7 +1106,7 @@ patternProperties:
>    "^minix,.*":
>      description: MINIX Technology Ltd.
>    "^mips,.*":
> -    description: MIPS Technology (deprecated, use 'mti' or 'img')
> +    description: MIPS Technology (deprecated, use 'mti', 'img', or 'gf')

This is starting to look a bit hilarious.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

>      deprecated: true
>    "^miramems,.*":
>      description: MiraMEMS Sensing Technology Co., Ltd.
> 
> -- 
> 2.43.0
> 
> 

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Re: [PATCH 3/9] dt-bindings: riscv: Add MIPS Boston board compatible

[Conor Dooley]

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On Mon, Sep 14, 2026 at 03:55:51PM +0200, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> 
> Document the MIPS Boston board compatible with a P8700 bitfile.
> 
> Co-developed-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>  Documentation/devicetree/bindings/riscv/gf.yaml | 27 +++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/gf.yaml b/Documentation/devicetree/bindings/riscv/gf.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..060910c9b04f482aee6f08f8f72232acbad118bb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/gf.yaml
> @@ -0,0 +1,27 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/gf.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: GlobalFoundries MIPS SoC-based boards
> +
> +maintainers:
> +  - Djordje Todorovic <djordje.todorovic@htecgroup.com>
> +  - Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> +
> +description:
> +  GlobalFoundries MIPS SoC-based boards
> +
> +properties:
> +  $nodename:
> +    const: '/'
> +  compatible:
> +    oneOf:
> +      - description: Boston FPGA development board with a MIPS P8700 bitfile

I'm not convinced that this is specific enough at all.
I have absolutely no idea from this description if there's even a
specific FPGA involved here - this could mean a bitstream used on an Altera
platform or a Xilinx one, with totally different contents.
I'm only happy with FPGA bitstream content being supported if it is
versioned strictly and matches with some clear and obvious releases from
the vendor. I cannot even find this board by googling it, let alone find
clear information about what this could correspond to.

> +        items:
> +          - const: gf,mips-p8700-boston

"items: - const" is the same as just having "const". SoC-specific
fallback is also missing, although in this case it'll be tricky to have
a meaningful one.

pw-bot: changes-requested

Thanks,
Conor.

> +
> +additionalProperties: true
> +
> +...
> 
> -- 
> 2.43.0
> 
> 

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Re: [PATCH 5/9] dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI

[Conor Dooley]

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On Mon, Sep 14, 2026 at 03:55:53PM +0200, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> 
> Document the aclint mswi compatible for the MIPS P8700 and
> introduce the 'riscv,hart-indexes' property,
> used to address the sparse MIPS P8700 harts.
> 
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>  .../thead,c900-aclint-mswi.yaml                    | 34 ++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
> index 62fd220e126e650e3800d8eee2a749fdbbde6108..47c04943eb0c793467aaa5570776605cae0eadfd 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
> @@ -17,6 +17,8 @@ properties:
>                - sophgo,sg2042-aclint-mswi
>                - sophgo,sg2044-aclint-mswi
>            - const: thead,c900-aclint-mswi
> +      - items:
> +          - const: gf,mips-p8700-aclint-mswi
>        - items:
>            - enum:
>                - anlogic,dr1v90-aclint-mswi
> @@ -29,6 +31,14 @@ properties:
>      minItems: 1
>      maxItems: 4095
>  
> +  riscv,hart-indexes:

Nothing in this binding is a ratified extension, despite how prevalent
the use has become, so I object to using riscv as a prefix for something
the other devices don't use.

I'm not very familiar with this spec, why do you need this and the
existing devices don't?
Why can the information not be looked up using the existing phandle?

> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    minItems: 1
> +    maxItems: 4095
> +    description:
> +      A list of hart indexes that the MSWI device uses to address each hart
> +      that is mentioned in the "interrupts-extended"
> +
>  additionalProperties: false
>  
>  required:
> @@ -36,6 +46,19 @@ required:
>    - reg
>    - interrupts-extended
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: gf,mips-p8700-aclint-mswi
> +    then:
> +      required:
> +        - riscv,hart-indexes
> +    else:
> +      properties:
> +        riscv,hart-indexes: false
> +
>  examples:
>    - |
>      interrupt-controller@94000000 {
> @@ -46,4 +69,15 @@ examples:
>                              <&cpu4intc 3>;
>        reg = <0x94000000 0x00010000>;
>      };
> +
> +  - |
> +    mswi@16150000 {
> +      compatible = "gf,mips-p8700-aclint-mswi";
> +      reg = <0x16150000 0x4000>;
> +      interrupts-extended = <&cpu1intc 3>,
> +                            <&cpu2intc 3>,
> +                            <&cpu3intc 3>,
> +                            <&cpu4intc 3>;
> +      riscv,hart-indexes = <0x0 0x1 0x10 0x11>;
> +    };
>  ...
> 
> -- 
> 2.43.0
> 
> 

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Re: [PATCH 4/9] dt-bindings: interrupt-controller: Add MIPS P8700 APLIC

[Conor Dooley]

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On Mon, Sep 14, 2026 at 03:55:52PM +0200, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> 
> Document the aplic compatible for the MIPS P8700.
> 
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>  Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
> index 0718071444d29fbfa36283fc9666e8cecd6f77e7..9b986aa1a1c62316a1fd08fe535075111601b80e 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
> @@ -27,6 +27,7 @@ properties:
>    compatible:
>      items:
>        - enum:
> +          - gf,mips-p8700-aplic

I'm also curious about why "mips" appears here. Isn't p8700-aplic
specific enough?

>            - qemu,aplic
>            - spacemit,k3-aplic
>        - const: riscv,aplic
> 
> -- 
> 2.43.0
> 
> 

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Re: [PATCH 1/9] dt-bindings: vendor-prefixes: Add GlobalFoundries, Inc.

[Maciej W. Rozycki]

On Tue, 15 Sep 2026, Conor Dooley wrote:

> > @@ -1104,7 +1106,7 @@ patternProperties:
> >    "^minix,.*":
> >      description: MINIX Technology Ltd.
> >    "^mips,.*":
> > -    description: MIPS Technology (deprecated, use 'mti' or 'img')
> > +    description: MIPS Technology (deprecated, use 'mti', 'img', or 'gf')
> 
> This is starting to look a bit hilarious.

 This should read "MIPS Technologies Inc." FWIW, as that's what the 
company used to be called (note the plural vs singular).

  Maciej

Re: [PATCH 3/9] dt-bindings: riscv: Add MIPS Boston board compatible

[Maciej W. Rozycki]

On Tue, 15 Sep 2026, Conor Dooley wrote:

> > +    oneOf:
> > +      - description: Boston FPGA development board with a MIPS P8700 bitfile
> 
> I'm not convinced that this is specific enough at all.
> I have absolutely no idea from this description if there's even a
> specific FPGA involved here - this could mean a bitstream used on an Altera
> platform or a Xilinx one, with totally different contents.
> I'm only happy with FPGA bitstream content being supported if it is
> versioned strictly and matches with some clear and obvious releases from
> the vendor. I cannot even find this board by googling it, let alone find
> clear information about what this could correspond to.

 This stuff has been around for a decade now; cf. commit 6e62a888029b 
("MIPS: generic: Support MIPS Boston development boards").  Public 
resources have been scarce.  Here's the best one I could track down: 
<https://training.mips.com/cps_mips/Examples/MD00901_Boot-MIPS_Example_Boot_Code_for_MIPS_Cores.pdf>.  
Expect disappointment, but at least there's a photo of the platform (p. 
142).

  Maciej