* [PATCH v2 01/18] ARM: dts: qcom: sdx55: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 02/18] arm64: dts: qcom: msm8996: " Krishna Chaitanya Chundru
` (17 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts
index d23b8ec08af4..0443a86899a9 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts
+++ b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts
@@ -249,7 +249,7 @@ &pcie_phy {
&pcie_rc {
perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie_default>;
pinctrl-names = "default";
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 02/18] arm64: dts: qcom: msm8996: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 01/18] ARM: dts: qcom: sdx55: Fix PCIe WAKE# GPIO polarity Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 03/18] arm64: dts: qcom: sdm845: " Krishna Chaitanya Chundru
` (16 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
index d55e4075040f..5b42c266557a 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
@@ -192,7 +192,7 @@ &mmcc {
&pcie0 {
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&pm8994_l28>;
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
index 77ad613590a3..2abcc733dad8 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
@@ -280,7 +280,7 @@ &pcie0 {
vdda-supply = <&vreg_l28a_0p925>;
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
};
&pcie_phy {
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 03/18] arm64: dts: qcom: sdm845: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 01/18] ARM: dts: qcom: sdx55: Fix PCIe WAKE# GPIO polarity Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 02/18] arm64: dts: qcom: msm8996: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 04/18] arm64: dts: qcom: sc8180x: " Krishna Chaitanya Chundru
` (15 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index 846138149b2c..3e636926231d 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -619,7 +619,7 @@ &mss_pil {
&pcie0 {
status = "okay";
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&pcie0_3p3v_dual>;
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 04/18] arm64: dts: qcom: sc8180x: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (2 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 03/18] arm64: dts: qcom: sdm845: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 05/18] arm64: dts: qcom: sm8150: " Krishna Chaitanya Chundru
` (14 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 +-
arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
index 565e5a9979b1..e6ab523d249e 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
@@ -492,7 +492,7 @@ &mdss_edp_out {
&pcie3 {
perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 180 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie3_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
index c10a936b320a..327dba55a5ec 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
@@ -593,7 +593,7 @@ &mdss_edp_out {
&pcie1 {
perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 177 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 05/18] arm64: dts: qcom: sm8150: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (3 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 04/18] arm64: dts: qcom: sc8180x: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 06/18] arm64: dts: qcom: sm8250: " Krishna Chaitanya Chundru
` (13 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 94a3b02cb289..74df5cd86f04 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1905,7 +1905,7 @@ pcie0: pcie@1c00000 {
phy-names = "pciephy";
perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
- wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 06/18] arm64: dts: qcom: sm8250: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (4 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 05/18] arm64: dts: qcom: sm8150: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 07/18] arm64: dts: qcom: sm8350: " Krishna Chaitanya Chundru
` (12 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 90f8b091634e..e0c357222bc7 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2211,7 +2211,7 @@ pcie0: pcie@1c00000 {
phy-names = "pciephy";
perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -2338,7 +2338,7 @@ pcie1: pcie@1c08000 {
phy-names = "pciephy";
perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
@@ -2465,7 +2465,7 @@ pcie2: pcie@1c10000 {
phy-names = "pciephy";
perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 07/18] arm64: dts: qcom: sm8350: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (5 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 06/18] arm64: dts: qcom: sm8250: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 08/18] arm64: dts: qcom: sm8450: " Krishna Chaitanya Chundru
` (11 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index bb93c3e9417b..e9b9e03f725e 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -500,7 +500,7 @@ &pcie0 {
pinctrl-0 = <&pcie0_default_state>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -514,7 +514,7 @@ &pcie0_phy {
&pcie1 {
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 08/18] arm64: dts: qcom: sm8450: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (6 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 07/18] arm64: dts: qcom: sm8350: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 09/18] arm64: dts: qcom: sm8550: " Krishna Chaitanya Chundru
` (10 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index b8793482b181..7bc5f85e7ebc 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2021,7 +2021,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
phy-names = "pciephy";
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -2186,7 +2186,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
phy-names = "pciephy";
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 09/18] arm64: dts: qcom: sm8550: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (7 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 08/18] arm64: dts: qcom: sm8450: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 10/18] arm64: dts: qcom: sm8650: " Krishna Chaitanya Chundru
` (9 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 2 +-
7 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
index ae301d78e071..aaf5eb57ce23 100644
--- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
@@ -336,7 +336,7 @@ &mdss_dsi0_phy {
&pcie0 {
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -349,7 +349,7 @@ &pcie0_phy {
&pcie1 {
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
index 9df8dcd6c62b..41b09ab43d0c 100644
--- a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
@@ -1045,7 +1045,7 @@ &mdss_dp0 {
&pcie0 {
vddpe-3v3-supply = <&pcie_upd_3p3>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
@@ -1146,7 +1146,7 @@ pci@0,1 {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 82fb10ed6b6b..4777c908c4d7 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -1087,7 +1087,7 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
@@ -1121,7 +1121,7 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 7c634572c6b7..eb1de33e5ba5 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -739,7 +739,7 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -756,7 +756,7 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 473ec4e27daf..13cdb5b0ce40 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -987,7 +987,7 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
index 81c02ee27fe9..cf4e4e9d9e26 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
@@ -510,7 +510,7 @@ &i2c_master_hub_0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
index 367f6eae5e65..9f347bea6c74 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
@@ -584,7 +584,7 @@ cirrus,gpio-ctrl2 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 10/18] arm64: dts: qcom: sm8650: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (8 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 09/18] arm64: dts: qcom: sm8550: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 11/18] arm64: dts: qcom: sm8750: " Krishna Chaitanya Chundru
` (8 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ++--
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
index 6ddf30ecabfe..668c183bc177 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
@@ -1074,7 +1074,7 @@ &mdss_dp0_out {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
@@ -1108,7 +1108,7 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
index 41d0c7edc433..b73ad7861eb4 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -1027,7 +1027,7 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
@@ -1061,7 +1061,7 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index 26045430d34a..1332c864801f 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -642,7 +642,7 @@ &mdss_dsi0_phy {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
@@ -659,7 +659,7 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index 1fb78588a504..2e874f046a0e 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -1021,7 +1021,7 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 11/18] arm64: dts: qcom: sm8750: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (9 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 10/18] arm64: dts: qcom: sm8650: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 12/18] arm64: dts: qcom: kaanapali: " Krishna Chaitanya Chundru
` (7 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
index 9b5fbc004df4..23476fbd993c 100644
--- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
@@ -1119,7 +1119,7 @@ &pcie0_phy {
};
&pcieport0 {
- wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>;
reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
wifi@0 {
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 12/18] arm64: dts: qcom: kaanapali: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (10 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 11/18] arm64: dts: qcom: sm8750: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 13/18] arm64: dts: qcom: sar2130p: " Krishna Chaitanya Chundru
` (6 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
index 6d817381bb37..83c4f93a654a 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
@@ -976,7 +976,7 @@ &pcie0_phy {
};
&pcie_port0 {
- wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>;
reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
wifi@0 {
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 13/18] arm64: dts: qcom: sar2130p: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (11 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 12/18] arm64: dts: qcom: kaanapali: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 14/18] arm64: dts: qcom: monaco: " Krishna Chaitanya Chundru
` (5 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
index 80428c0b3b4e..7469134f42b7 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
+++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
@@ -358,7 +358,7 @@ &i2c10 {
&pcie0 {
perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 14/18] arm64: dts: qcom: monaco: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (12 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 13/18] arm64: dts: qcom: sar2130p: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 15/18] arm64: dts: qcom: lemans: " Krishna Chaitanya Chundru
` (4 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/monaco-evk.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
index 9d17ef7d2caf..b30fc7ecdf32 100644
--- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts
@@ -643,12 +643,12 @@ &pcie1_phy {
&pcieport0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
};
&pcieport1 {
reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
};
&pmm8620au_0_gpios {
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
index 1ff39530ea3d..2472df47a0ea 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
@@ -615,7 +615,7 @@ &pcie0 {
&pcieport0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1103";
@@ -651,7 +651,7 @@ &pcie1 {
&pcieport1 {
reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
};
&pcie1_phy {
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 15/18] arm64: dts: qcom: lemans: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (13 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 14/18] arm64: dts: qcom: monaco: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 16/18] arm64: dts: qcom: talos: " Krishna Chaitanya Chundru
` (3 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans-evk.dts | 4 ++--
arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts
index a45485b54a5b..194e114a12a0 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk.dts
+++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts
@@ -840,7 +840,7 @@ &mdss0_dp1_phy {
&pcie0 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -857,7 +857,7 @@ &pcie0_phy {
&pcie1 {
perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
index 144f117ba511..3ecf3d464dd7 100644
--- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
@@ -962,7 +962,7 @@ wake-pins {
&pcie0 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -972,7 +972,7 @@ &pcie0 {
&pcie1 {
perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 16/18] arm64: dts: qcom: talos: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (14 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 15/18] arm64: dts: qcom: lemans: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 17/18] arm64: dts: qcom: sa8540p-ride: " Krishna Chaitanya Chundru
` (2 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +-
arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index 047b4efb04b9..43f110ba3a7c 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -445,7 +445,7 @@ &mdss_dsi0_phy {
&pcie {
perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
index a31bed7fad07..198f656bddf1 100644
--- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
@@ -367,7 +367,7 @@ &mdss_dsi0_phy {
&pcie {
perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie_default_state>;
pinctrl-names = "default";
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 17/18] arm64: dts: qcom: sa8540p-ride: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (15 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 16/18] arm64: dts: qcom: talos: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-17 11:54 ` [PATCH v2 18/18] arm64: dts: qcom: kodiak: " Krishna Chaitanya Chundru
2026-09-29 3:14 ` (subset) [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Bjorn Andersson
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index c72faaa0ae7a..e85d78ecac2e 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -374,7 +374,7 @@ &pcie2a {
&pcie2a_port0 {
reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
};
&pcie2a_phy {
@@ -397,7 +397,7 @@ &pcie3a {
&pcie3a_port0 {
reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
};
&pcie3a_phy {
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 18/18] arm64: dts: qcom: kodiak: Fix PCIe WAKE# GPIO polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (16 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 17/18] arm64: dts: qcom: sa8540p-ride: " Krishna Chaitanya Chundru
@ 2026-09-17 11:54 ` Krishna Chaitanya Chundru
2026-09-29 3:14 ` (subset) [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Bjorn Andersson
18 siblings, 0 replies; 20+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 11:54 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Krishna Chaitanya Chundru, linux-arm-msm, devicetree,
linux-kernel, konrad.dybcio, mani
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 3 ++-
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 2 +-
arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts | 4 ++--
5 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
index 5bb33a8a9830..509fc4941a02 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
@@ -558,7 +558,7 @@ &pcie0_phy {
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
};
&pcie1 {
@@ -579,6 +579,7 @@ &pcie1_phy {
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
};
&pmk8350_adc_tm {
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 41d60c87f5bd..ed0b81710b9a 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -541,7 +541,7 @@ &pcie0_phy {
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
};
&pcie1 {
@@ -571,7 +571,7 @@ &pcie1_phy {
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
};
&pm7325_gpios {
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
index 31bafa2cf51d..6527cf815b85 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
@@ -705,7 +705,7 @@ &pcie0_phy {
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
};
&pcie1 {
@@ -736,7 +736,7 @@ &pcie1_phy {
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
pcie@0,0 {
compatible = "pci1179,0623";
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
index 13e8e62f6205..4ac2998a0a6a 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
@@ -833,7 +833,7 @@ &pcie0_phy {
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
};
&pcie1 {
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts b/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts
index 4f2e0109f49b..141d263e6566 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts
@@ -653,7 +653,7 @@ &ice {
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
pinctrl-names = "default";
@@ -670,7 +670,7 @@ &pcie0_phy {
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
pinctrl-names = "default";
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: (subset) [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity
2026-09-17 11:54 [PATCH v2 00/18] arm64: dts: qcom: Fix wake-gpios polarity Krishna Chaitanya Chundru
` (17 preceding siblings ...)
2026-09-17 11:54 ` [PATCH v2 18/18] arm64: dts: qcom: kodiak: " Krishna Chaitanya Chundru
@ 2026-09-29 3:14 ` Bjorn Andersson
18 siblings, 0 replies; 20+ messages in thread
From: Bjorn Andersson @ 2026-09-29 3:14 UTC (permalink / raw)
To: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krishna Chaitanya Chundru
Cc: linux-arm-msm, devicetree, linux-kernel, konrad.dybcio, mani
On Thu, 17 Sep 2026 17:24:08 +0530, Krishna Chaitanya Chundru wrote:
> PCIe wake is active low signal as per the PCIe base spec, Several Qualcomm
> platform devicetrees incorrectly describe wake-gpios as GPIO_ACTIVE_HIGH.
>
> This series fixes the wake-gpios polarity by using GPIO_ACTIVE_LOW
> instead of GPIO_ACTIVE_HIGH.
>
> Tested on Talos Ride & lemans evk platform.
>
> [...]
Applied, thanks!
[15/18] arm64: dts: qcom: lemans: Fix PCIe WAKE# GPIO polarity
commit: cd8d4803bba672a4d03ce508fc9d2c459eb85c55
[16/18] arm64: dts: qcom: talos: Fix PCIe WAKE# GPIO polarity
commit: e622c5d6553b8a83af04115c87f006406baf2675
[17/18] arm64: dts: qcom: sa8540p-ride: Fix PCIe WAKE# GPIO polarity
commit: 450a0bfdb1b66da50ef98eefe1ff45b7be21e9a7
[18/18] arm64: dts: qcom: kodiak: Fix PCIe WAKE# GPIO polarity
commit: b2b980536b5a4a5420175dfbef7f481408761b7b
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 20+ messages in thread