From: Dapeng Mi <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>, Zide Chen <zide.chen@intel.com>,
Falcon Thomas <thomas.falcon@intel.com>,
Xudong Hao <xudong.hao@intel.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>
Subject: [PATCH 09/12] perf/x86/intel: Constrain PantherCove UOPS_DISPATCHED events
Date: Thu, 17 Sep 2026 09:52:31 +0800 [thread overview]
Message-ID: <20260917015234.981153-10-dapeng1.mi@linux.intel.com> (raw)
In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com>
Per the latest PantherCove event definitions, the following events are
only supported on PMCs 0-3:
- UOPS_DISPATCHED.INT_EU_ALL (0x1b2)
- UOPS_DISPATCHED.ALU (0x2b2)
Add explicit event constraints for these two events so scheduling does
not place them on unsupported counters.
Fixes: d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR")
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index e6efd2a2ada6..9462862bf72a 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -506,6 +506,8 @@ static struct event_constraint intel_pnc_event_constraints[] = {
INTEL_EVENT_CONSTRAINT(0xce, 0x1),
INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
+ INTEL_UEVENT_CONSTRAINT(0x01b2, 0xf),
+ INTEL_UEVENT_CONSTRAINT(0x02b2, 0xf),
INTEL_UEVENT_CONSTRAINT(0x0847, 0xf),
INTEL_UEVENT_CONSTRAINT(0x0446, 0xf),
INTEL_UEVENT_CONSTRAINT(0x0846, 0xf),
--
2.34.1
next prev parent reply other threads:[~2026-09-17 2:00 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-17 1:52 [PATCH 00/12] perf/x86/intel: PEBS data-source fixes and OMR updates Dapeng Mi
2026-09-17 1:52 ` [PATCH 01/12] perf/x86/intel: Fix GRT PEBS load/store direction for latency events Dapeng Mi
2026-09-17 1:52 ` [PATCH 02/12] perf/x86/intel: Fix CMT " Dapeng Mi
2026-09-17 1:52 ` [PATCH 03/12] perf/x86/intel: Fix DKT " Dapeng Mi
2026-09-17 1:52 ` [PATCH 04/12] perf/x86/intel: Update arw_latency_data() mem-op direction handling Dapeng Mi
2026-09-17 1:52 ` [PATCH 05/12] perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints Dapeng Mi
2026-09-17 1:52 ` [PATCH 06/12] perf/x86/intel: Remove incorrect PantherCove " Dapeng Mi
2026-09-17 1:52 ` [PATCH 07/12] perf/x86/intel: Correct Panther cove data source snoop states Dapeng Mi
2026-09-17 1:52 ` [PATCH 08/12] perf/x86/intel: Delete dead NVL PEBS data-source init call Dapeng Mi
2026-09-17 1:52 ` Dapeng Mi [this message]
2026-09-17 1:52 ` [PATCH 10/12] perf/x86/intel: Add precise OMR event support for DMR/NVL Dapeng Mi
2026-09-17 1:52 ` [PATCH 11/12] perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rsp Dapeng Mi
2026-09-17 1:52 ` [PATCH 12/12] perf/x86/intel: Rename NVL " Dapeng Mi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260917015234.981153-10-dapeng1.mi@linux.intel.com \
--to=dapeng1.mi@linux.intel.com \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=ak@linux.intel.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=dapeng1.mi@intel.com \
--cc=eranian@google.com \
--cc=irogers@google.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
--cc=thomas.falcon@intel.com \
--cc=xudong.hao@intel.com \
--cc=zide.chen@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®