From: Dapeng Mi <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>, Zide Chen <zide.chen@intel.com>,
Falcon Thomas <thomas.falcon@intel.com>,
Xudong Hao <xudong.hao@intel.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>
Subject: [PATCH 07/12] perf/x86/intel: Correct Panther cove data source snoop states
Date: Thu, 17 Sep 2026 09:52:29 +0800 [thread overview]
Message-ID: <20260917015234.981153-8-dapeng1.mi@linux.intel.com> (raw)
In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com>
For Panthercove, the snoop states for the data source encodings
"Prefetch Promotion" and "Cross Core Prefetch Promotion" should be
SNOOP_NONE instead of SNOOP_MISS.
Correct the incorrect snooping states for Panther cove.
Fixes: d2bdcde9626c ("perf/x86/intel: Add support for PEBS memory auxiliary info field in DMR")
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/ds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 7a67fb675b43..24ec9bc63d2d 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -277,8 +277,8 @@ static u64 pnc_pebs_l2_hit_data_source[PNC_PEBS_DATA_SOURCE_MAX] = {
0, /* 0x06: Reserved */
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT), /* 0x07: L2 Hit Snoop HIT */
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM), /* 0x08: L2 Hit Snoop Hit Modified */
- OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, MISS), /* 0x09: Prefetch Promotion */
- OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, MISS), /* 0x0a: Cross Core Prefetch Promotion */
+ OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x09: Prefetch Promotion */
+ OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x0a: Cross Core Prefetch Promotion */
0, /* 0x0b: Reserved */
0, /* 0x0c: Reserved */
0, /* 0x0d: Reserved */
--
2.34.1
next prev parent reply other threads:[~2026-09-17 2:00 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-17 1:52 [PATCH 00/12] perf/x86/intel: PEBS data-source fixes and OMR updates Dapeng Mi
2026-09-17 1:52 ` [PATCH 01/12] perf/x86/intel: Fix GRT PEBS load/store direction for latency events Dapeng Mi
2026-09-17 1:52 ` [PATCH 02/12] perf/x86/intel: Fix CMT " Dapeng Mi
2026-09-17 1:52 ` [PATCH 03/12] perf/x86/intel: Fix DKT " Dapeng Mi
2026-09-17 1:52 ` [PATCH 04/12] perf/x86/intel: Update arw_latency_data() mem-op direction handling Dapeng Mi
2026-09-17 1:52 ` [PATCH 05/12] perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints Dapeng Mi
2026-09-17 1:52 ` [PATCH 06/12] perf/x86/intel: Remove incorrect PantherCove " Dapeng Mi
2026-09-17 1:52 ` Dapeng Mi [this message]
2026-09-17 1:52 ` [PATCH 08/12] perf/x86/intel: Delete dead NVL PEBS data-source init call Dapeng Mi
2026-09-17 1:52 ` [PATCH 09/12] perf/x86/intel: Constrain PantherCove UOPS_DISPATCHED events Dapeng Mi
2026-09-17 1:52 ` [PATCH 10/12] perf/x86/intel: Add precise OMR event support for DMR/NVL Dapeng Mi
2026-09-17 1:52 ` [PATCH 11/12] perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rsp Dapeng Mi
2026-09-17 1:52 ` [PATCH 12/12] perf/x86/intel: Rename NVL " Dapeng Mi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260917015234.981153-8-dapeng1.mi@linux.intel.com \
--to=dapeng1.mi@linux.intel.com \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=ak@linux.intel.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=dapeng1.mi@intel.com \
--cc=eranian@google.com \
--cc=irogers@google.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
--cc=thomas.falcon@intel.com \
--cc=xudong.hao@intel.com \
--cc=zide.chen@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®