[PATCH v6 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus

[PATCH v6 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus

[Andrea Righi]

NVIDIA Olympus implements SMT with two symmetric processing elements (PEs).
When only one PE is active, the core operates in single-thread mode and that PE
can use the full core resources. When both PEs are active, the core operates in
two-thread mode and the PEs share those resources. This behavior is common to
SMT implementations, but Olympus is particularly sensitive to brief sibling
activations because returning from two-thread mode to single-thread mode after a
sibling becomes idle is not immediate.  As described by commit 293f9611ae735
("sched/fair: Prefer fully idle cores for NOHZ balancing"):

  Briefly activating an otherwise idle sibling can reduce the
  performance available to the other sibling and this effect does not
  necessarily end once the activated sibling becomes idle: after the ILB
  finishes and its CPU enters WFI, full single-thread performance is
  restored only after the sibling has remained idle for a qualification
  interval (10 Ki cycles on the tested Vera system).

That change prevents the NOHZ idle load balancer from unnecessarily waking a
sibling of a busy PE. However, ordinary task placement can still select either
sibling of an idle core. Repeatedly changing the active PE can therefore keep
Olympus cores in two-thread mode despite little or no useful overlap between the
siblings.

The first patch teaches the fair scheduler's idle-selection paths to honor
SD_ASYM_PACKING at the shared-capacity SMT level. The scheduler first selects a
candidate CPU and core according to its existing placement and capacity rules,
then chooses the highest-priority available sibling within that core. This also
completes the existing POWER7 SD_ASYM_PACKING behavior by applying its
hardware-thread ordering during idle selection.

Olympus firmware does not currently provide an interface to describe the
preferred SMT sibling. Adding such a firmware or ACPI interface will take time
and will not help systems with existing firmware. At the same time, inferring
this policy from MIDR would encode a platform-specific decision in the kernel
and make it harder to replace with a proper firmware ABI.

The second patch therefore adds the sched_smt_asym_packing= boot option. Using
sched_smt_asym_packing=on explicitly opts the SMT scheduling domain into
SD_ASYM_PACKING without requiring architecture-specific detection. Priority
remains defined by arch_asym_cpu_priority(). The weak default orders siblings by
-cpu, consistently selecting the lowest-numbered available logical CPU.
Architecture overrides remain authoritative, so siblings assigned equal
priorities remain unordered. The default auto mode preserves
architecture-provided topology policy, including the existing powerpc behavior,
while off provides an explicit override to disable SMT asymmetric packing.

On Olympus, PE0 and PE1 have equal steady-state capacity; this preference does
not identify a faster PE. The lower-numbered logical CPU is used only as a
canonical choice when both siblings are available. Consistently selecting the
same sibling avoids alternating the active PE across wakeups, lets the other
sibling remain idle for longer, and allows more cores to remain in, or return
to, full-resource single-thread mode.

The v6 series was tested on a two-node Vera system using 88-thread
single-precision GEMM workloads on the 88 physical cores of NUMA node 0, with
sched_smt_asym_packing=on and the workloads allowed to choose either sibling of
every core. Each result covers five runs.

Two BLAS implementations were tested: OpenBLAS, an open-source BLAS library that
provides a publicly reproducible benchmark, and NVIDIA Performance Libraries
(NVPL), NVIDIA's optimized BLAS implementation.

OpenBLAS was evaluated using benchmark/sgemm.goto with an M=N=K=16384
single-precision GEMM. NVPL was evaluated using benchblas with the same matrix
dimensions, non-transposed inputs, alpha=1 and beta=0. The numbers below are the
mean and standard deviation from five runs.

OpenBLAS throughput increased from 7.11876 +/- 0.06734 TFLOP/s on the baseline
kernel to 7.34669 +/- 0.01936 TFLOP/s with this series (+3.20%). NVPL throughput
increased from 9.64742 +/- 0.17311 TFLOP/s to 10.29695 +/- 0.01786 TFLOP/s
(+6.73%).

The lower standard deviation also shows that the results became more
predictable. With the series applied, the workloads consistently settled on the
lower-numbered sibling, allowing the other sibling to remain idle.

Changes in v6:
 - Drop the arm64 MIDR-based enablement and arch_asym_cpu_priority()
   override (Will Deacon)
 - Add the generic sched_smt_asym_packing={auto,on,off} boot option
 - Use the default -cpu priority ordering instead of interpreting MPIDR
 - Drop the SMT-specific asymmetric-packing static key and use
   sched_smt_active() (Vincent Guittot)
 - Link to v5: https://lore.kernel.org/r/20260909062649.469633-1-arighi@nvidia.com

Changes in v5:
 - Remove the redundant olympus_prefer_pe0 state (K Prateek Nayak)
 - Link to v4: https://lore.kernel.org/r/20260908082345.103087-1-arighi@nvidia.com

Changes in v4:
 - Honor the SMT sibling priority in the slow path (Srikar Dronamraju)
 - Rename the consolidated helper to select_idle_smt_cpu()
   (Srikar Dronamraju)
 - Link to v3: https://lore.kernel.org/r/20260907163513.4172411-1-arighi@nvidia.com

Changes in v3:
 - Consolidate the SMT-priority adjustment in select_idle_sibling()
   after an idle candidate has been selected (K Prateek Nayak)
 - Fold the asym SMT checks into select_idle_smt_priority() and scan the
   scheduling-domain span directly (K Prateek Nayak)
 - Link to v2: https://lore.kernel.org/r/20260904091838.3617894-1-arighi@nvidia.com

Changes in v2:
 - Clarify that the generic scheduler change also covers POWER7
   (Dietmar Eggemann)
 - Simplify sched_smt_asym_prefer() by inspecting the lowest scheduling
   domain directly (Dietmar Eggemann)
 - Link to v1: https://lore.kernel.org/r/20260831181800.1668646-1-arighi@nvidia.com

Andrea Righi (2):
      sched/fair: Honor asymmetric SMT priority in idle selection
      sched/topology: Add asymmetric SMT packing override

 Documentation/admin-guide/kernel-parameters.txt | 11 ++++
 kernel/sched/fair.c                             | 85 ++++++++++++++++++++-----
 kernel/sched/topology.c                         | 49 ++++++++++++++
 3 files changed, 128 insertions(+), 17 deletions(-)

[PATCH 1/2] sched/fair: Honor asymmetric SMT priority in idle selection

[Andrea Righi]

POWER7 uses SD_ASYM_PACKING at the shared-capacity SMT level to order
hardware threads, and NVIDIA Olympus benefits from the same policy. Idle
CPU selection does not consult that order, so a task can wake on an
arbitrary sibling and remain there until load balancing corrects the
placement. On these systems, that initial choice can prevent the core
from entering its preferred lower-thread resource mode and cause a large
and persistent performance loss.

When idle selection finds an available CPU in an SMT core, choose the
highest-priority available sibling. On SMT2 Olympus this only changes
selection on fully idle cores. A partially idle core has only one
available CPU. On wider SMT systems such as POWER7, it also fills
available siblings in priority order while the core is partially busy.

Apply the preference to idle-core and idle-CPU scans,
asymmetric-capacity scans, target, previous, recently-used CPU fast
paths and the slow path. Inspect the lowest scheduling domain directly,
but require both CPUs to share its span because isolcpus can split
hardware siblings across scheduling domains.

Keep physical-core capacity selection independent from SMT sibling
ordering. SD_ASYM_CPUCAPACITY first selects among cores with different
maximum capacities, then SD_ASYM_PACKING selects the preferred available
sibling inside the chosen core, whose siblings continue to share equal
capacity.

Reviewed-by: Srikar Dronamraju <srikar@linux.ibm.com>
Reviewed-by: K Prateek Nayak <kprateek.nayak@amd.com>
Tested-by: K Prateek Nayak <kprateek.nayak@amd.com>
Signed-off-by: Andrea Righi <arighi@nvidia.com>
---
 kernel/sched/fair.c | 85 ++++++++++++++++++++++++++++++++++++---------
 1 file changed, 68 insertions(+), 17 deletions(-)

diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index 4d0b94465d19e..8e6dc3a657cca 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -8598,6 +8598,35 @@ static inline bool test_idle_cores(int cpu)
 	return false;
 }
 
+/*
+ * Redirect a CPU to a higher-priority available sibling in its SMT domain,
+ * subject to task affinity.
+ */
+static inline int select_idle_smt_cpu(struct task_struct *p, int cpu)
+{
+	struct sched_domain *sd;
+	int best = cpu;
+	int sibling;
+
+	if (!sched_smt_active())
+		return cpu;
+
+	sd = rcu_dereference_all(cpu_rq(cpu)->sd);
+	if (!sd || !(sd->flags & SD_SHARE_CPUCAPACITY) ||
+	    !(sd->flags & SD_ASYM_PACKING))
+		return cpu;
+
+	for_each_cpu_and(sibling, sched_domain_span(sd), p->cpus_ptr) {
+		if (sibling == best || !choose_idle_cpu(sibling, p))
+			continue;
+
+		if (sched_asym_prefer(sibling, best))
+			best = sibling;
+	}
+
+	return best;
+}
+
 /*
  * Scans the local SMT mask to see if the entire core is idle, and records this
  * information in sd_balance_shared->has_idle_cores.
@@ -8982,7 +9011,7 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 
 	if (choose_idle_cpu(target, p) &&
 	    asym_fits_cpu(task_util, util_min, util_max, target))
-		return target;
+		goto select_smt_priority;
 
 	/*
 	 * If the previous CPU is cache affine and idle, don't be stupid:
@@ -8992,8 +9021,10 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 	    asym_fits_cpu(task_util, util_min, util_max, prev)) {
 
 		if (!static_branch_unlikely(&sched_cluster_active) ||
-		    cpus_share_resources(prev, target))
-			return prev;
+		    cpus_share_resources(prev, target)) {
+			target = prev;
+			goto select_smt_priority;
+		}
 
 		prev_aff = prev;
 	}
@@ -9011,7 +9042,8 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 	    prev == smp_processor_id() &&
 	    this_rq()->nr_running <= 1 &&
 	    asym_fits_cpu(task_util, util_min, util_max, prev)) {
-		return prev;
+		target = prev;
+		goto select_smt_priority;
 	}
 
 	/* Check a recently used CPU as a potential idle candidate: */
@@ -9025,8 +9057,10 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 	    asym_fits_cpu(task_util, util_min, util_max, recent_used_cpu)) {
 
 		if (!static_branch_unlikely(&sched_cluster_active) ||
-		    cpus_share_resources(recent_used_cpu, target))
-			return recent_used_cpu;
+		    cpus_share_resources(recent_used_cpu, target)) {
+			target = recent_used_cpu;
+			goto select_smt_priority;
+		}
 
 	} else {
 		recent_used_cpu = -1;
@@ -9048,7 +9082,11 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 		 */
 		if (sd) {
 			i = select_idle_capacity(p, sd, target);
-			return ((unsigned)i < nr_cpumask_bits) ? i : target;
+			if ((unsigned int)i < nr_cpumask_bits) {
+				target = i;
+				goto select_smt_priority;
+			}
+			return target;
 		}
 	}
 
@@ -9061,14 +9099,18 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 
 		if (!has_idle_core && cpus_share_cache(prev, target)) {
 			i = select_idle_smt(p, sd, prev);
-			if ((unsigned int)i < nr_cpumask_bits)
-				return i;
+			if ((unsigned int)i < nr_cpumask_bits) {
+				target = i;
+				goto select_smt_priority;
+			}
 		}
 	}
 
 	i = select_idle_cpu(p, sd, has_idle_core, target);
-	if ((unsigned)i < nr_cpumask_bits)
-		return i;
+	if ((unsigned int)i < nr_cpumask_bits) {
+		target = i;
+		goto select_smt_priority;
+	}
 
 	/*
 	 * For cluster machines which have lower sharing cache like L2 or
@@ -9076,12 +9118,19 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 	 * first. But prev_cpu or recent_used_cpu may also be a good candidate,
 	 * use them if possible when no idle CPU found in select_idle_cpu().
 	 */
-	if ((unsigned int)prev_aff < nr_cpumask_bits)
-		return prev_aff;
-	if ((unsigned int)recent_used_cpu < nr_cpumask_bits)
-		return recent_used_cpu;
+	if ((unsigned int)prev_aff < nr_cpumask_bits) {
+		target = prev_aff;
+		goto select_smt_priority;
+	}
+	if ((unsigned int)recent_used_cpu < nr_cpumask_bits) {
+		target = recent_used_cpu;
+		goto select_smt_priority;
+	}
 
 	return target;
+
+select_smt_priority:
+	return select_idle_smt_cpu(p, target);
 }
 
 /**
@@ -9758,8 +9807,10 @@ select_task_rq_fair(struct task_struct *p, int prev_cpu, int wake_flags)
 	}
 
 	/* Slow path */
-	if (unlikely(sd))
-		return sched_balance_find_dst_cpu(sd, p, cpu, prev_cpu, sd_flag);
+	if (unlikely(sd)) {
+		new_cpu = sched_balance_find_dst_cpu(sd, p, cpu, prev_cpu, sd_flag);
+		return select_idle_smt_cpu(p, new_cpu);
+	}
 
 	/* Fast path */
 	if (wake_flags & WF_TTWU)
-- 
2.55.0

[PATCH 2/2] sched/topology: Add asymmetric SMT packing override

[Andrea Righi]

Architectures can use SD_ASYM_PACKING to describe preferred CPU ordering
at the SMT scheduling domain. Some systems benefit from the same policy,
but their firmware cannot currently describe the preference. Inferring
it from the CPU model would embed a platform-specific policy in the
kernel.

Add the sched_smt_asym_packing boot option to override SD_ASYM_PACKING
at the SMT level. Accept auto, on and off. Auto preserves the
architecture-provided topology and is also the default when the option
is absent. On and off force the flag without changing asymmetric packing
at higher topology levels.

Apply the override centrally to domains with SD_SHARE_CPUCAPACITY so it
also covers architectures with custom SMT topology callbacks, including
powerpc. When forced on, priority remains defined by
arch_asym_cpu_priority(). The weak default prefers lower-numbered
logical CPUs, while architecture overrides remain authoritative.
Siblings with equal priorities remain unordered.

Signed-off-by: Andrea Righi <arighi@nvidia.com>
---
 .../admin-guide/kernel-parameters.txt         | 11 +++++
 kernel/sched/topology.c                       | 49 +++++++++++++++++++
 2 files changed, 60 insertions(+)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 33cd30996e47e..36c3b2e563441 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -6799,6 +6799,17 @@ Kernel parameters
 			solution to mutex-based priority inversion.
 			Format: <bool>
 
+	sched_smt_asym_packing= [KNL,SMP]
+			Override asymmetric packing at the SMT scheduling domain.
+			Format: { auto | on | off }
+			auto: Preserve the architecture default. This is the
+			default when the option is omitted.
+			on: Force asymmetric packing at the SMT scheduling domain.
+			Idle CPU selection prefers siblings with a higher
+			architecture-defined priority. Siblings with equal
+			priorities remain unordered.
+			off: Ignore SMT sibling priorities.
+
 	sched_verbose	[KNL,EARLY] Enables verbose scheduler debug messages.
 
 	schedstats=	[KNL,X86] Enable or disable scheduled statistics.
diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c
index 0248227d983a7..cdfcecf673fd7 100644
--- a/kernel/sched/topology.c
+++ b/kernel/sched/topology.c
@@ -32,6 +32,46 @@ static int __init sched_debug_setup(char *str)
 }
 early_param("sched_verbose", sched_debug_setup);
 
+#ifdef CONFIG_SCHED_SMT
+enum sched_smt_asym_packing_mode {
+	SCHED_SMT_ASYM_PACKING_AUTO,
+	SCHED_SMT_ASYM_PACKING_ON,
+	SCHED_SMT_ASYM_PACKING_OFF,
+	SCHED_SMT_ASYM_PACKING_NR,
+};
+
+static enum sched_smt_asym_packing_mode sched_smt_asym_packing __read_mostly =
+	SCHED_SMT_ASYM_PACKING_AUTO;
+
+static const char * const sched_smt_asym_packing_modes[SCHED_SMT_ASYM_PACKING_NR] = {
+	[SCHED_SMT_ASYM_PACKING_AUTO]	= "auto",
+	[SCHED_SMT_ASYM_PACKING_ON]	= "on",
+	[SCHED_SMT_ASYM_PACKING_OFF]	= "off",
+};
+
+static int __init sched_smt_asym_packing_parse(const char *str)
+{
+	for (int mode = 0; mode < SCHED_SMT_ASYM_PACKING_NR; mode++) {
+		if (!strcmp(str, sched_smt_asym_packing_modes[mode]))
+			return mode;
+	}
+
+	return -EINVAL;
+}
+
+static int __init setup_sched_smt_asym_packing(char *str)
+{
+	int mode = sched_smt_asym_packing_parse(str);
+
+	if (mode < 0)
+		return 0;
+
+	sched_smt_asym_packing = mode;
+	return 1;
+}
+__setup("sched_smt_asym_packing=", setup_sched_smt_asym_packing);
+#endif
+
 static inline bool sched_debug(void)
 {
 	return sched_debug_verbose;
@@ -1950,6 +1990,15 @@ sd_init(struct sched_domain_topology_level *tl,
 	if (WARN_ONCE(sd_flags & ~TOPOLOGY_SD_FLAGS,
 		      "wrong sd_flags in topology description\n"))
 		sd_flags &= TOPOLOGY_SD_FLAGS;
+#ifdef CONFIG_SCHED_SMT
+	if (sd_flags & SD_SHARE_CPUCAPACITY) {
+		if (sched_smt_asym_packing == SCHED_SMT_ASYM_PACKING_ON)
+			sd_flags |= SD_ASYM_PACKING;
+		else if (sched_smt_asym_packing ==
+			 SCHED_SMT_ASYM_PACKING_OFF)
+			sd_flags &= ~SD_ASYM_PACKING;
+	}
+#endif
 	sd_flags |= asym_cpu_capacity_classify(sd_span, cpu_map);
 
 	*sd = (struct sched_domain){
-- 
2.55.0

Re: [PATCH 1/2] sched/fair: Honor asymmetric SMT priority in idle selection

[Kayra Cizmeci]

Hi Andrea,

Hope I ain't got anything wrong, I'm a bit sick.

> POWER7 uses SD_ASYM_PACKING at the shared-capacity SMT level to order
> hardware threads, and NVIDIA Olympus benefits from the same policy. Idle
> CPU selection does not consult that order, so a task can wake on an
> arbitrary sibling and remain there until load balancing corrects the
> placement. On these systems, that initial choice can prevent the core
> from entering its preferred lower-thread resource mode and cause a large
> and persistent performance loss.

> When idle selection finds an available CPU in an SMT core, choose the
> highest-priority available sibling. On SMT2 Olympus this only changes
> selection on fully idle cores. A partially idle core has only one
> available CPU. On wider SMT systems such as POWER7, it also fills
> available siblings in priority order while the core is partially busy.

> Apply the preference to idle-core and idle-CPU scans,
> asymmetric-capacity scans, target, previous, recently-used CPU fast
> paths and the slow path. Inspect the lowest scheduling domain directly,
> but require both CPUs to share its span because isolcpus can split
> hardware siblings across scheduling domains.

> Keep physical-core capacity selection independent from SMT sibling
> ordering. SD_ASYM_CPUCAPACITY first selects among cores with different
> maximum capacities, then SD_ASYM_PACKING selects the preferred available
> sibling inside the chosen core, whose siblings continue to share equal
> capacity.


> +/*
> + * Redirect a CPU to a higher-priority available sibling in its SMT domain,
> + * subject to task affinity.
> + */
> +static inline int select_idle_smt_cpu(struct task_struct *p, int cpu)
> +{
> +	struct sched_domain *sd;
> +	int best = cpu;
> +	int sibling;
> +
> +	if (!sched_smt_active())
> +		return cpu;
> +
> +	sd = rcu_dereference_all(cpu_rq(cpu)->sd);
> +	if (!sd || !(sd->flags & SD_SHARE_CPUCAPACITY) ||
> +	    !(sd->flags & SD_ASYM_PACKING))
> +		return cpu;
> +
> +	for_each_cpu_and(sibling, sched_domain_span(sd), p->cpus_ptr) {
> +		if (sibling == best || !choose_idle_cpu(sibling, p))
> +			continue;
> +
> +		if (sched_asym_prefer(sibling, best))
> +			best = sibling;
> +	}
> +
> +	return best;
> +}

> @@ -9061,14 +9099,18 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
>  
>  		if (!has_idle_core && cpus_share_cache(prev, target)) {
>  			i = select_idle_smt(p, sd, prev);
> -			if ((unsigned int)i < nr_cpumask_bits)
> -				return i;
> +			if ((unsigned int)i < nr_cpumask_bits) {
> +				target = i;
> +				goto select_smt_priority;
> +			}
>  		}
>  	}

The sched_smt_active() check on select_idle_smt_cpu seems to be redundant on here.

We could remove this
By moving the check on select_idle_smt_cpu() to goto block and
adding one check before the select_idle_smt_cpu() on select_task_rq_fair(). And just calling
select_idle_smt_cpu() on here.

I also have a question, do we need select_idle_smt() call on here? If yes then why? I was really confused while reading.

Thanks,
Kayra :_:

Re: [PATCH 1/2] sched/fair: Honor asymmetric SMT priority in idle selection

[Kayra Cizmeci]

> Hi Andrea,

> Hope I ain't got anything wrong, I'm a bit sick.


> The sched_smt_active() check on select_idle_smt_cpu seems to be redundant on here.

> We could remove this
> By moving the check on select_idle_smt_cpu() to goto block and
> adding one check before the select_idle_smt_cpu() on select_task_rq_fair(). And just calling
> select_idle_smt_cpu() on here.

> I also have a question, do we need select_idle_smt() call on here? If yes then why? I was really confused while reading.

> Thanks,
> Kayra :_:

After I don't know how much times of reading the same functions, I finally understand.
Because of has_idle_core is false, we search if there are any idle SMP's on 
any of the cores.

I normally was going to send this alot earlier, but I fall asleep after
realizing this.

Also now, I don't think we need to remove the checks for one place. It complicates things,
when I tried.

I also booted the patch, it did not worked on me since I just have a regular SMT2.
So, that was the waited behavior.

So, here's this:
Tested-by: Kayra Cizmeci <kayracizmeci@gmail.com>

Annnddddddddddddddddddddddddddddddd....

This: 
Reviewed-by: Kayra Cizmeci <kayracizmeci@gmail.com>

Thanks,
Kayra :-)