* [PATCH v4 1/3] dt-bindings: misc: introduce pci1179,0220.yaml
2026-09-18 15:26 [PATCH v4 0/3] PCI: introduce TC9564 misc driver Alex Elder
@ 2026-09-18 15:26 ` Alex Elder
2026-09-18 15:26 ` [PATCH v4 2/3] misc: tc9564: introduce base PCI driver Alex Elder
2026-09-18 15:26 ` [PATCH v4 3/3] arm64: dts: qcom: qcs6490-rb3gen2: add endpoint buses Alex Elder
2 siblings, 0 replies; 6+ messages in thread
From: Alex Elder @ 2026-09-18 15:26 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, arnd, gregkh, bhelgaas, andersson,
konradybcio, abelvesa
Cc: daniel, mohd.anwar, lorenzo.bianconi, devicetree, linux-pci,
linux-arm-msm, linux-kernel
Define the binding for the Toshiba TC9564 PCI endpoint function device.
The third downstream PCIe switch port within this chip has an embedded
PCIe controller, and that implements two of these PCIe functions.
Multiple internal components are accessed via PCI function BARs, as
indicated in the diagram below. This is facilitated by the use of the
devicetree pci-ep-bus mechanism, and is demonstrated in the example.
Co-developed-by: Daniel Thompson <daniel@riscstar.com>
Signed-off-by: Daniel Thompson <daniel@riscstar.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
---
v4: - Dropped pci-ep-bus@0 node from the example
.../bindings/misc/pci1179,0220.yaml | 146 ++++++++++++++++++
MAINTAINERS | 6 +
2 files changed, 152 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/pci1179,0220.yaml
diff --git a/Documentation/devicetree/bindings/misc/pci1179,0220.yaml b/Documentation/devicetree/bindings/misc/pci1179,0220.yaml
new file mode 100644
index 0000000000000..c92c8d3d33f76
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/pci1179,0220.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/pci1179,0220.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba TC9564 internal PCI endpoint function
+
+maintainers:
+ - Alex Elder <elder@kernel.org>
+ - Daniel Thompson <danielt@kernel.org>
+
+description: >
+ The Toshiba TC9564 is specialized SoC that implements a PCIe switch
+ as well as an Ethernet AVB/TSN bridge. In addition to these, the SoC
+ implements other functions, including a reset and clock controller,
+ an address translation unit, and a few other devices.
+
+ The PCI switch has three downstream ports. The first two are exposed
+ externally, while the third is used by an internal PCIe endpoint. The
+ internal endpoint implements two PCIe functions, and attached to each
+ of these is a 10 Gbps capable Synopsys Ethernet controller and an
+ interrupt controller that converts internal "wired" interrupts into
+ MSIs delivered to the host.
+
+ PCIe BARs provide access to registers that manage almost all IP blocks.
+ The SoC is modeled using a PCI endpoint bus. The IP blocks are bound
+ to platform drivers that access the hardware using MMIO through the
+ PCI BARs.
+
+ ------------------------------------
+ | Host |
+ -----........---------------...-----
+ | | | |
+ | PCIe | |I2C|
+ | | | |
+ ----------+........+-------------+...+-------------------------------
+ | |upstream| | | ---------------- |
+ | Toshiba | Port 0 | | +-------+ PCIe pwrctrl | |
+ | TC9564 ----++---- | I2C | ---------------- |
+ | SoC || |controller| ---------------- |
+ | || | +-------+ GPIO | |
+ | || | | | controller | |
+ | ------++------ ------------ ---------------- |
+ | | US | |
+ | | | ---------------------------------------- |
+ | | DS3+====+ downstream port 3 | |
+ | | | |--------------------------------------| |
+ | | PCIe | | embedded PCIe endpoint | |
+ | | switch | |~~~~~~~~~~~~~~~~~~~++~~~~~~~~~~~~~~~~~| |
+ | | | | PCIe function 0 || PCIe function 1 | |
+ | | | |-------------------||-----------------| |
+ | | | | BAR || BAR || BAR || BAR | BAR | BAR | |
+ | | | | 0 || 2 || 4 || 0 | 2 | 4 | |
+ | | DS1 DS2 | ---.------.------.--++--------------.--- |
+ | --++------++-- : : : : |
+ | || || : ---.-- :....... : |
+ | || || : |SRAM| : : : |
+ | || || : ------ : ---.--- : |
+ | || || : ....: |clock| ....: |
+ | || || : : : ------- : : |
+ | || || ------.---- -.- : -.- : |
+ | || || |translate| |M| :....... |M| : |
+ | || || ----------- |S| : : |S| : |
+ | || || |I| : ---.--- |I| : |
+ | || || |G| : |reset| |G| : |
+ | || || |E| : ------- |E| : |
+ | --------++-- --++-------- |N| : |N| : |
+ | |downstream| |downstream| ------.---- ------.---- |
+ | | port 1 | | port 2 | | XGMAC 0 | | XGMAC 1 | |
+ --+..........+--+..........+----------+.......+-----------+.....+----
+ | | | |
+ |USXGMII| |SGMII|
+ | | | |
+ --+.......+-- ---+.....+---
+ | Ethernet | | Ethernet |
+ | PHY | | PHY |
+ ------------- -------------
+
+allOf:
+ - $ref: /schemas/pci/pci-ep-bus.yaml
+
+properties:
+ compatible:
+ const: pci1179,0220 # Toshiba TC9564 (a.k.a. Qualcomm QPS615)
+
+ reg:
+ maxItems: 1
+ description: PCI Bus/Device/Function config space address
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - ranges
+
+examples:
+ - |
+ pcie@0,0 {
+ reg = <0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x83000000 0x0 0x0 0x0 0x0 0x1fd00000>;
+
+ dev@0,0 {
+ compatible = "pci1179,0220";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ /* Ranges will be updated dynamically */
+ ranges = <0x0 0x0 0x0 0x83000000 0x0 0x0 0x0 0x4000>,
+ <0x2 0x0 0x0 0x83000000 0x0 0x4000 0x0 0x80000>,
+ <0x4 0x0 0x0 0x83000000 0x0 0x84000 0x0 0x200000>;
+
+ pci-ep-bus@4 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* Map 0x0-0x1fffff to BAR 4 */
+ ranges = <0x0 0x4 0x0 0x0 0x200000>;
+ };
+ };
+
+ dev@0,1 {
+ compatible = "pci1179,0220";
+ reg = <0x100 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ /* Ranges will be updated dynamically */
+ ranges = <0x0 0x0 0x0 0x83000100 0x0 0x0 0x0 0x4000>,
+ <0x2 0x0 0x0 0x83000100 0x0 0x4000 0x0 0x80000>,
+ <0x4 0x0 0x0 0x83000100 0x0 0x84000 0x0 0x200000>;
+
+ pci-ep-bus@4 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* Map 0x0-0x1fffff to BAR 4 */
+ ranges = <0x0 0x4 0x0 0x0 0x200000>;
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 6096dab7121e8..aa6b805e1ab2b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -27670,6 +27670,12 @@ F: Documentation/devicetree/bindings/media/i2c/toshiba,tc358743.txt
F: drivers/media/i2c/tc358743*
F: include/media/i2c/tc358743.h
+TOSHIBA TC9564 PCI DRIVER
+M: Alex Elder <elder@kernel.org>
+M: Daniel Thompson <danielt@kernel.org>
+S: Maintained
+F: Documentation/devicetree/bindings/misc/pci1179,0220.yaml
+
TOSHIBA WMI HOTKEYS DRIVER
M: Azael Avalos <coproscefalo@gmail.com>
L: platform-driver-x86@vger.kernel.org
--
2.53.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v4 2/3] misc: tc9564: introduce base PCI driver
2026-09-18 15:26 [PATCH v4 0/3] PCI: introduce TC9564 misc driver Alex Elder
2026-09-18 15:26 ` [PATCH v4 1/3] dt-bindings: misc: introduce pci1179,0220.yaml Alex Elder
@ 2026-09-18 15:26 ` Alex Elder
2026-09-18 17:30 ` Bjorn Helgaas
2026-09-18 15:26 ` [PATCH v4 3/3] arm64: dts: qcom: qcs6490-rb3gen2: add endpoint buses Alex Elder
2 siblings, 1 reply; 6+ messages in thread
From: Alex Elder @ 2026-09-18 15:26 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, arnd, gregkh, bhelgaas, andersson,
konradybcio, abelvesa
Cc: daniel, mohd.anwar, lorenzo.bianconi, devicetree, linux-pci,
linux-arm-msm, linux-kernel
The Toshiba TC9564 is small and highly-specialized SoC that implements
a PCIe switch as well as an Ethernet AVB/TSN bridge. In addition to
these, the SoC implements other functions, including a reset and clock
controller, an address translation unit, and a few other devices. PCIe
BARs provide access to registers that manage these IP blocks, and the
SoC is modeled using a PCI endpoint bus in devicetree. This allows the
IP blocks to be bound to platform drivers that do MMIO via the PCI BARs.
Create a new PCI driver under drivers/misc that binds with the embedded
PCI endpoint functions within the TC9564 SoC. Because these functions
will use devicetree pci-ep-bus to provide access to other IP blocks
within the TC9564 chip, the main purpose of this driver is to do basic
PCI initialization, then call of_platform_default_populate() to scan for
the any endpoint bus children, and probe all devices defined therein.
Because we're using pci-ep-bus, we need to use the PCI quirks mechanism
to have of_pci_make_dev_node() be called for each endpoint device in
pci_bus_add_device() (via pci_fixup_device(pci_fixup_final, dev)).
Co-developed-by: Daniel Thompson <daniel@riscstar.com>
Signed-off-by: Daniel Thompson <daniel@riscstar.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
---
v4: - Refined the definition of the TC9564_PCI Kconfig entry
- Now use pci_enable_device() rather than pcim_enable_device()
MAINTAINERS | 1 +
drivers/misc/Kconfig | 15 +++++++
drivers/misc/Makefile | 1 +
drivers/misc/tc9564-pci.c | 84 +++++++++++++++++++++++++++++++++++++++
drivers/pci/quirks.c | 1 +
5 files changed, 102 insertions(+)
create mode 100644 drivers/misc/tc9564-pci.c
diff --git a/MAINTAINERS b/MAINTAINERS
index aa6b805e1ab2b..cf846853fdc79 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -27675,6 +27675,7 @@ M: Alex Elder <elder@kernel.org>
M: Daniel Thompson <danielt@kernel.org>
S: Maintained
F: Documentation/devicetree/bindings/misc/pci1179,0220.yaml
+F: drivers/misc/tc9564-pci.c
TOSHIBA WMI HOTKEYS DRIVER
M: Azael Avalos <coproscefalo@gmail.com>
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 7364931dad3a1..9c5b1e9d672e8 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -568,6 +568,21 @@ config MCHP_LAN966X_PCI
- lan966x-miim (MDIO_MSCC_MIIM)
- lan966x-switch (LAN966X_SWITCH)
+config TC9564_PCI
+ tristate "Toshiba TC9564 PCI function support"
+ depends on OF
+ depends on PCI
+ select PCI_DYNAMIC_OF_NODES
+ select PCI_QUIRKS
+ default m
+ help
+ This enables support for two PCI functions implemented by the
+ embedded PCIe endpoint in the Toshiba TC9564 SoC. A platform
+ driver uses a pci-ep-bus node in devicetree to provide MMIO
+ access to other SoC devices through PCI function BARs. A PCI
+ quirk causes the ranges property in the endpoint's devicetree
+ node to be updated dynamically.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index e8d8d5d88c0df..7cc3d615d37a4 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -71,3 +71,4 @@ obj-y += keba/
obj-y += amd-sbi/
obj-$(CONFIG_MISC_RP1) += rp1/
obj-$(CONFIG_INTEL_SSEI) += issei/
+obj-$(CONFIG_TC9564_PCI) += tc9564-pci.o
diff --git a/drivers/misc/tc9564-pci.c b/drivers/misc/tc9564-pci.c
new file mode 100644
index 0000000000000..e4d00dfecfca9
--- /dev/null
+++ b/drivers/misc/tc9564-pci.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright (C) 2026 by RISCstar Solutions Corporation. All rights reserved.
+ */
+
+/*
+ * The Toshiba TC9564 implements a PCIe Gen 3 switch that connects an
+ * upstream x4 port to three downstream PCIe ports. Two of the downstream
+ * ports are external, and the third is internal, implementing a PCIe
+ * endpoint which implements two PCIe functions. Each PCIe function drives
+ * a Synopsys XGMAC Ethernet interface capable of 10 Gbps operation.
+ *
+ * The TC9564 implements other functionality, including an embedded MCU,
+ * a UART, a GPIO controller, a reset controller, a clock controller, and
+ * interrupt handling. These features are separate from (and in some
+ * cases used by) both Ethernet XGMACs. Each Ethernet MAC must be
+ * attached to a working PHY for it to be functional, and for this
+ * reason either of them (or both!) might not be usable/used.
+ *
+ * This PCI driver binds to the Toshiba TC9564 (physical) PCI function
+ * (VID 0x1179, DID 0x0220).
+ */
+
+#include <linux/device.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+
+static void tc9564_function_remove(struct pci_dev *pdev)
+{
+ of_platform_depopulate(&pdev->dev);
+ pci_clear_master(pdev);
+ pci_disable_device(pdev);
+}
+
+static int
+tc9564_function_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np;
+ int ret;
+
+ /* Despite being a PCI device, we require devicetree */
+ np = dev_of_node(dev);
+ if (!np)
+ return dev_err_probe(dev, -EINVAL, "no devicetree node\n");
+
+ ret = pci_enable_device(pdev);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to enable device\n");
+
+ pci_set_master(pdev);
+
+ /* Scan for pci-ep-bus (simple-bus) nodes and probe their sub-devices */
+ ret = of_platform_default_populate(np, NULL, dev);
+ if (ret)
+ goto err_depopulate;
+
+ return 0;
+
+err_depopulate:
+ tc9564_function_remove(pdev);
+
+ return dev_err_probe(dev, ret, "failed to populate platform bus\n");
+}
+
+static const struct pci_device_id tc9564_function_id_table[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA, 0x0220), },
+ { },
+};
+MODULE_DEVICE_TABLE(pci, tc9564_function_id_table);
+
+static struct pci_driver tc9564_function_driver = {
+ .name = KBUILD_MODNAME,
+ .id_table = tc9564_function_id_table,
+ .probe = tc9564_function_probe,
+ .remove = tc9564_function_remove,
+};
+module_pci_driver(tc9564_function_driver);
+
+MODULE_DESCRIPTION("Toshiba TC9564 PCIe Embedded Function Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index de9bbccda21fd..54e310c4153df 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -6391,6 +6391,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA, 0x0220, of_pci_make_dev_node);
/*
* Devices known to require a longer delay before first config space access
--
2.53.0
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v4 2/3] misc: tc9564: introduce base PCI driver
2026-09-18 15:26 ` [PATCH v4 2/3] misc: tc9564: introduce base PCI driver Alex Elder
@ 2026-09-18 17:30 ` Bjorn Helgaas
2026-09-18 17:49 ` Alex Elder
0 siblings, 1 reply; 6+ messages in thread
From: Bjorn Helgaas @ 2026-09-18 17:30 UTC (permalink / raw)
To: Alex Elder
Cc: robh, krzk+dt, conor+dt, arnd, gregkh, bhelgaas, andersson,
konradybcio, abelvesa, daniel, mohd.anwar, lorenzo.bianconi,
devicetree, linux-pci, linux-arm-msm, linux-kernel,
Andrea della Porta, Herve Codina, Lizhi Hou
[+cc Andrea, Herve, Lizhi for of_pci_make_dev_node() quirks]
On Fri, Sep 18, 2026 at 10:26:57AM -0500, Alex Elder wrote:
> The Toshiba TC9564 is small and highly-specialized SoC that implements
> a PCIe switch as well as an Ethernet AVB/TSN bridge. In addition to
> these, the SoC implements other functions, including a reset and clock
> controller, an address translation unit, and a few other devices. PCIe
> BARs provide access to registers that manage these IP blocks, and the
> SoC is modeled using a PCI endpoint bus in devicetree. This allows the
> IP blocks to be bound to platform drivers that do MMIO via the PCI BARs.
>
> Create a new PCI driver under drivers/misc that binds with the embedded
> PCI endpoint functions within the TC9564 SoC. Because these functions
> will use devicetree pci-ep-bus to provide access to other IP blocks
> within the TC9564 chip, the main purpose of this driver is to do basic
> PCI initialization, then call of_platform_default_populate() to scan for
> the any endpoint bus children, and probe all devices defined therein.
>
> Because we're using pci-ep-bus, we need to use the PCI quirks mechanism
> to have of_pci_make_dev_node() be called for each endpoint device in
> pci_bus_add_device() (via pci_fixup_device(pci_fixup_final, dev)).
>
> Co-developed-by: Daniel Thompson <daniel@riscstar.com>
> Signed-off-by: Daniel Thompson <daniel@riscstar.com>
> Signed-off-by: Alex Elder <elder@riscstar.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com> # quirks.c
Not an issue for this patch, but I'm not sure the quirk mechanism is
the best mechanism for doing this. It's not working around a device
defect like most quirks do.
I wonder if pci_bus_add_device() should unconditionally call a wrapper
that calls of_pci_make_dev_node() for bridges and any device that
appears in an allow-list. I guess it sort of amounts to the same
thing in the end, but it might be a little more explicit and not
subject to CONFIG_PCI_QUIRKS.
> +++ b/drivers/pci/quirks.c
> @@ -6391,6 +6391,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA, 0x0220, of_pci_make_dev_node);
>
> /*
> * Devices known to require a longer delay before first config space access
> --
> 2.53.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 2/3] misc: tc9564: introduce base PCI driver
2026-09-18 17:30 ` Bjorn Helgaas
@ 2026-09-18 17:49 ` Alex Elder
0 siblings, 0 replies; 6+ messages in thread
From: Alex Elder @ 2026-09-18 17:49 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: robh, krzk+dt, conor+dt, arnd, gregkh, bhelgaas, andersson,
konradybcio, abelvesa, daniel, mohd.anwar, lorenzo.bianconi,
devicetree, linux-pci, linux-arm-msm, linux-kernel,
Andrea della Porta, Herve Codina, Lizhi Hou
On 9/18/26 12:30 PM, Bjorn Helgaas wrote:
> [+cc Andrea, Herve, Lizhi for of_pci_make_dev_node() quirks]
>
> On Fri, Sep 18, 2026 at 10:26:57AM -0500, Alex Elder wrote:
>> The Toshiba TC9564 is small and highly-specialized SoC that implements
>> a PCIe switch as well as an Ethernet AVB/TSN bridge. In addition to
>> these, the SoC implements other functions, including a reset and clock
>> controller, an address translation unit, and a few other devices. PCIe
>> BARs provide access to registers that manage these IP blocks, and the
>> SoC is modeled using a PCI endpoint bus in devicetree. This allows the
>> IP blocks to be bound to platform drivers that do MMIO via the PCI BARs.
>>
>> Create a new PCI driver under drivers/misc that binds with the embedded
>> PCI endpoint functions within the TC9564 SoC. Because these functions
>> will use devicetree pci-ep-bus to provide access to other IP blocks
>> within the TC9564 chip, the main purpose of this driver is to do basic
>> PCI initialization, then call of_platform_default_populate() to scan for
>> the any endpoint bus children, and probe all devices defined therein.
>>
>> Because we're using pci-ep-bus, we need to use the PCI quirks mechanism
>> to have of_pci_make_dev_node() be called for each endpoint device in
>> pci_bus_add_device() (via pci_fixup_device(pci_fixup_final, dev)).
>>
>> Co-developed-by: Daniel Thompson <daniel@riscstar.com>
>> Signed-off-by: Daniel Thompson <daniel@riscstar.com>
>> Signed-off-by: Alex Elder <elder@riscstar.com>
>
> Acked-by: Bjorn Helgaas <bhelgaas@google.com> # quirks.c
>
> Not an issue for this patch, but I'm not sure the quirk mechanism is
> the best mechanism for doing this. It's not working around a device
> defect like most quirks do.
I pretty much agree with you. I think I mentioned this before
(though it might have been in a private conversation) that it
is an intentional act to call of_pci_make_dev_node() for an
endpoint (and not just a bridge). And that's different from
a hardware quirk. You only need to do it if there's a pci-ep-bus
sub-node on the endpoint. (I'd have to verify this on the other
users of this approach to be 100% sure though.)
> I wonder if pci_bus_add_device() should unconditionally call a wrapper
> that calls of_pci_make_dev_node() for bridges and any device that
> appears in an allow-list. I guess it sort of amounts to the same
> thing in the end, but it might be a little more explicit and not
> subject to CONFIG_PCI_QUIRKS.
Yes, I think it would be better to separate this case from PCI
quirks, which are really intended for anomalous hardware behavior.
I'd like to get these things merged, but would be willing to work
on this sort of thing (and/or on separating this driver type, as
Arnd suggested elsewhere).
Thanks a lot Bjorn.
-Alex
>> +++ b/drivers/pci/quirks.c
>> @@ -6391,6 +6391,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
>> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
>> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
>> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node);
>> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA, 0x0220, of_pci_make_dev_node);
>>
>> /*
>> * Devices known to require a longer delay before first config space access
>> --
>> 2.53.0
>>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 3/3] arm64: dts: qcom: qcs6490-rb3gen2: add endpoint buses
2026-09-18 15:26 [PATCH v4 0/3] PCI: introduce TC9564 misc driver Alex Elder
2026-09-18 15:26 ` [PATCH v4 1/3] dt-bindings: misc: introduce pci1179,0220.yaml Alex Elder
2026-09-18 15:26 ` [PATCH v4 2/3] misc: tc9564: introduce base PCI driver Alex Elder
@ 2026-09-18 15:26 ` Alex Elder
2 siblings, 0 replies; 6+ messages in thread
From: Alex Elder @ 2026-09-18 15:26 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, arnd, gregkh, bhelgaas, andersson,
konradybcio, abelvesa
Cc: daniel, mohd.anwar, lorenzo.bianconi, devicetree, linux-pci,
linux-arm-msm, linux-kernel
The TC9564 SoC incorporates a PCIe switch, which is connected via
the second PCI segment (0001) on the RB3gen2 platform. The third
downstream port of that switch (pcie@3,0) has an embedded PCIe
endpoint that implements two PCIe functions.
The SoC implements other peripherals, and they will be accessed via
PCI endpoint bus. Define the devicetree nodes representing these
buses, including the mapping of each BAR's address range to its
local address space.
The endpoint's ranges property must be defined, but it will be
updated dynamically to include all BARs. As a result of this update,
the parent address portion of each range will reflect the specific
address assigned to the BAR.
Co-developed-by: Daniel Thompson <daniel@riscstar.com>
Signed-off-by: Daniel Thompson <daniel@riscstar.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
---
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 30 ++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 3bb5fca8e2b13..5b7f5292a8864 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -955,11 +955,41 @@ pcie@3,0 {
bus-range = <0x5 0xff>;
dev@0,0 {
+ compatible = "pci1179,0220";
reg = <0x50000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ /* Ranges will be updated dynamically */
+ ranges = <0x0 0x0 0x0 0x83050000 0x0 0x0 0x0 0x4000>,
+ <0x2 0x0 0x0 0x83050000 0x0 0x4000 0x0 0x80000>,
+ <0x4 0x0 0x0 0x83050000 0x0 0x84000 0x0 0x200000>;
+
+ pci-ep-bus@4 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* Map 0x0-0x1fffff to BAR 4 */
+ ranges = <0x0 0x4 0x0 0x0 0x200000>;
+ };
};
dev@0,1 {
+ compatible = "pci1179,0220";
reg = <0x50100 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ /* Ranges will be updated dynamically */
+ ranges = <0x0 0x0 0x0 0x83050100 0x0 0x0 0x0 0x4000>,
+ <0x2 0x0 0x0 0x83050100 0x0 0x4000 0x0 0x80000>,
+ <0x4 0x0 0x0 0x83050100 0x0 0x84000 0x0 0x200000>;
+
+ pci-ep-bus@4 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* Map 0x0-0x1fffff to BAR 4 */
+ ranges = <0x0 0x4 0x0 0x0 0x200000>;
+ };
};
};
};
--
2.53.0
^ permalink raw reply [flat|nested] 6+ messages in thread