[PATCH v6 0/3] arm: dts: altera: add Draeger M48 CPU Module

[PATCH v6 0/3] arm: dts: altera: add Draeger M48 CPU Module

[Petko Manolov]

Adding the device trees for “Dräger M48 on NXP i.MX6 (Q) and Intel/Altera
SoCFPGA Cyclone V” board variant.  It has both (the SoC and FPGA) on the same
carrier and they are cross-monitoring each other.

This is the SoCFPGA devicetree part.

Petko Manolov (3):
  dt-bindings: vendor-prefixes: add Draeger AG
  dt-bindings: arm: altera: add Draeger M48 Module
  arm: dts: altera: add Draeger M48 CPU Module

 .../devicetree/bindings/arm/altera.yaml       |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/arm/boot/dts/intel/socfpga/Makefile      |   1 +
 .../socfpga/socfpga_cyclone5_draeger_m48.dts  | 123 ++++++++++++++++++
 4 files changed, 127 insertions(+)
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts

-- 
2.47.3

[PATCH v6 1/3] dt-bindings: vendor-prefixes: add Draeger AG

[Petko Manolov]

Add a vendor prefix for Draegar AG, which is Draegerwerk AG & Co. KGaA
Link: https://www.draeger.com/de_de/Home

Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ba2002969373..276d62b848d5 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -467,6 +467,8 @@ patternProperties:
     description: DPTechnics
   "^dptel,.*":
     description: Guangdong Dapu Telecom Co., Ltd.
+  "^draeger,.*":
+    description: Draegerwerk AG & Co. KGaA
   "^dragino,.*":
     description: Dragino Technology Co., Limited
   "^dream,.*":
-- 
2.47.3

[PATCH v6 2/3] dt-bindings: arm: altera: add Draeger M48 Module

[Petko Manolov]

Add DT compatible string for Draeger's M48 CPU Module that is also
based on Altera SoCFPGA.

Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
---
 Documentation/devicetree/bindings/arm/altera.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 3030cf46fe74..e1e4bba248ad 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -47,6 +47,7 @@ properties:
           - enum:
               - altr,socfpga-cyclone5-socdk
               - denx,mcvevk
+              - draeger,m48
               - ebv,socrates
               - macnica,sodia
               - novtech,chameleon96
-- 
2.47.3

[PATCH v6 3/3] arm: dts: altera: add Draeger M48 CPU Module

[Petko Manolov]

Draeger M48 CPU Module that is built around Altera SoCFPGA.

Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
---
 arch/arm/boot/dts/intel/socfpga/Makefile      |   1 +
 .../socfpga/socfpga_cyclone5_draeger_m48.dts  | 123 ++++++++++++++++++
 2 files changed, 124 insertions(+)
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts

diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile
index 8df0976da01c..cdcea11abdfa 100644
--- a/arch/arm/boot/dts/intel/socfpga/Makefile
+++ b/arch/arm/boot/dts/intel/socfpga/Makefile
@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
 	socfpga_arria10_mercury_aa1_st1_emmc.dtb \
 	socfpga_arria10_mercury_aa1_st1_qspi.dtb \
 	socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \
+	socfpga_cyclone5_draeger_m48.dtb \
 	socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \
 	socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \
 	socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
new file mode 100644
index 000000000000..dae809c02adb
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2020 Draeger and Licensors, info@draeger.com
+ */
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "Draeger M48 Cyclone V SoC";
+	compatible = "draeger,m48", "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+
+	aliases {
+		/* this allow the ethaddr uboot environmnet variable contents
+		 * to be added to the gmac0 device tree blob.
+		 */
+		ethernet0 = &gmac0;
+	};
+
+	soc {
+		gpio3: gpio@ff202000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff202000 0x20>;
+
+			portd: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <2>;
+				reg = <0>;
+			};
+		};
+
+		gpio4: gpio@ff202020 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff202020 0x20>;
+
+			porte: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <2>;
+				reg = <0>;
+			};
+		};
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	rxc-skew-ps = <1860>;
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	rxdv-skew-ps = <0>;
+	txc-skew-ps = <900>;
+	txd0-skew-ps = <0>;
+	txd1-skew-ps = <0>;
+	txd2-skew-ps = <0>;
+	txd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	eeprom_mac: eeprom@50 {
+		compatible = "atmel,24c08";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
+&mmc0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+
+	flash: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		reg = <0>;
+
+		/* chip select */
+		spi-max-frequency = <100000000>;
+		m25p,fast-read;
+		cdns,read-delay = <4>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+	};
+};
-- 
2.47.3

Re: [PATCH v6 1/3] dt-bindings: vendor-prefixes: add Draeger AG

[Krzysztof Kozlowski]

On Thu, Sep 17, 2026 at 07:31:54PM +0300, Petko Manolov wrote:
> Add a vendor prefix for Draegar AG, which is Draegerwerk AG & Co. KGaA
> Link: https://www.draeger.com/de_de/Home
> 
> Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>

<form letter>
This is a friendly reminder during the review process.

It looks like you received a tag and forgot to add it.

If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions of patchset, under or above your Signed-off-by tag, unless
patch changed significantly (e.g. new properties added to the DT
bindings). Tag is "received", when provided in a message replied to you
on the mailing list. Tools like b4 can help here. However, there's no
need to repost patches *only* to add the tags. The upstream maintainer
will do that for tags received on the version they apply.

Please read:
https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577

If a tag was not added on purpose, please state in the patch changelog
or cover letter why and what changed.
</form letter>

Best regards,
Krzysztof

Re: [PATCH v6 2/3] dt-bindings: arm: altera: add Draeger M48 Module

[Krzysztof Kozlowski]

On Thu, Sep 17, 2026 at 07:31:55PM +0300, Petko Manolov wrote:
> Add DT compatible string for Draeger's M48 CPU Module that is also
> based on Altera SoCFPGA.

CPU modules almost never can be alone, thus this is incomplete. You need
the final board compatible. SoM could be a fallback. See NXP bindings
how it is doing for example.

Best regards,
Krzysztof

Re: [PATCH v6 3/3] arm: dts: altera: add Draeger M48 CPU Module

[Krzysztof Kozlowski]

On Thu, Sep 17, 2026 at 07:31:56PM +0300, Petko Manolov wrote:
> Draeger M48 CPU Module that is built around Altera SoCFPGA.

How can you run a CPU module alone? To my knowledge there is only one
such case, only one exception, and it was explained by the authors. If
this is second, I already asked you to properly explain the hardware in
commit msg.

Your sentence above explains nothing.

Best regards,
Krzysztof

Re: [PATCH v6 2/3] dt-bindings: arm: altera: add Draeger M48 Module

[Petko Manolov]

On 26-09-18 13:55:58, Krzysztof Kozlowski wrote:
> On Thu, Sep 17, 2026 at 07:31:55PM +0300, Petko Manolov wrote:
> > Add DT compatible string for Draeger's M48 CPU Module that is also based on
> > Altera SoCFPGA.
> 
> CPU modules almost never can be alone, thus this is incomplete. You need the
> final board compatible. SoM could be a fallback. See NXP bindings how it is
> doing for example.

Module is perhaps not the best of choice for this board, but to avoid duplicity
please read my next reply.


		Petko

Re: [PATCH v6 3/3] arm: dts: altera: add Draeger M48 CPU Module

[Petko Manolov]

On 26-09-18 13:57:22, Krzysztof Kozlowski wrote:
> On Thu, Sep 17, 2026 at 07:31:56PM +0300, Petko Manolov wrote:
> > Draeger M48 CPU Module that is built around Altera SoCFPGA.
> 
> How can you run a CPU module alone? To my knowledge there is only one such
> case, only one exception, and it was explained by the authors. If this is
> second, I already asked you to properly explain the hardware in commit msg.

I've described the board/carrier/module/whatever in the cover letter.  When i
put the same text in the commit message Sashiko rejected the patch on the
grounds that there should be just one CPU architecture there.  But there are
two.

> Your sentence above explains nothing.

Pleases read the above.  And now the explanation.

I'll try to describe the board once again.  Draeger folks are CCed so they can
correct me where i'm wrong.

This is a _proprietary_ board that consist of a carrier where the peripheral
devices live and SoM (hence 'module') where the _two_ SoCs live.  As i've
mentioned at least five times already, the imx6 and socfpga work _independently_
of each other but do _monitor_ each other constantly.  If one of the players
detect that the other one misbehaves or malfunctioned due to software or
hardware error, the respective, healthy SoC, takes over.

In this regard there's no _primary_ SoC as the other is capable of performing
the same tasks.  This is a heterogeneous board/module/younameit that is based on
two SoCs.  This is also not so uncommon in the industry.

This is where i am at right now:

	a) if i mention imx6 in the commit message of Altera socfpga binding or
	.dts Sashiko gets mad at me and rejects the patch;

	b) if i remove imx6 of the said commit you yell at me;

	c) M48 is a proprietary board with just one user - Draeger; 

I agree that my patches should not break the existing _semantic_ rules and they
should be refined before being accepted.

However, i do not understand why is it so hard for you to grasp the M48 concept
and apply some logic instead of stubbornness.  The commit message is not perfect
- how big of a deal is it?  Will it break anything important?  Either help me
make the commit message perfect or just accept it as it is.  We've already
wasted so much time on this stupid dts...


		Petko

Re: [PATCH v6 3/3] arm: dts: altera: add Draeger M48 CPU Module

[Krzysztof Kozlowski]

On 20/09/2026 09:59, Petko Manolov wrote:
> On 26-09-18 13:57:22, Krzysztof Kozlowski wrote:
>> On Thu, Sep 17, 2026 at 07:31:56PM +0300, Petko Manolov wrote:
>>> Draeger M48 CPU Module that is built around Altera SoCFPGA.
>>
>> How can you run a CPU module alone? To my knowledge there is only one such
>> case, only one exception, and it was explained by the authors. If this is
>> second, I already asked you to properly explain the hardware in commit msg.
> 
> I've described the board/carrier/module/whatever in the cover letter.  When i

Cover letters do not matter. We don't read them and they usually do not
end up in the git history. Your commit must stand on its own, not rely
on cover letter.

> put the same text in the commit message Sashiko rejected the patch on the
> grounds that there should be just one CPU architecture there.  But there are
> two.

Sashiko cannot reject a patch. Does not have such abilities nor power.

Regardless its comment was right - your description was between
incomplete to confusing.


Best regards,
Krzysztof