From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: Lorenzo Pieralisi <lpieralisi@kernel.org>,
Krzysztof Wilczynski <kwilczynski@kernel.org>,
Manivannan Sadhasivam <mani@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
<linux-pci@vger.kernel.org>
Cc: Rob Herring <robh@kernel.org>,
Thierry Reding <thierry.reding@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Frank Li <Frank.Li@kernel.org>, Vidya Sagar <vidyas@nvidia.com>,
Niklas Cassel <cassel@kernel.org>,
Koichiro Den <den@valinux.co.jp>,
Marco Crivellari <marco.crivellari@suse.com>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
"Manikanta Maddireddy" <mmaddireddy@nvidia.com>
Subject: [PATCH 09/11] PCI: tegra194: Balance core monitor clock on failures
Date: Wed, 23 Sep 2026 12:52:35 +0530 [thread overview]
Message-ID: <20260923072237.1139013-10-mmaddireddy@nvidia.com> (raw)
In-Reply-To: <20260923072237.1139013-1-mmaddireddy@nvidia.com>
tegra_pcie_dw_host_init() enables core_clk_m, but failure paths that leave
after the host init callback can unconfigure the controller without
disabling that clock. The enable error is also only logged, so later
cleanup can try to disable a clock that was never enabled.
Track the monitor clock state, return enable failures, and use a common
helper on retry, remove, suspend, shutdown and host-init failure paths so
the clock is disabled exactly when it was enabled.
Fixes: a86ca8698c88 ("PCI: tegra194: Add core monitor clock support")
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
drivers/pci/controller/dwc/pcie-tegra194.c | 33 ++++++++++++++++++----
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 637779993c40..9b337dbada70 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -246,6 +246,7 @@ struct tegra_pcie_dw {
void __iomem *appl_base;
struct clk *core_clk;
struct clk *core_clk_m;
+ bool core_clk_m_enabled;
struct reset_control *core_apb_rst;
struct reset_control *core_rst;
struct dw_pcie pci;
@@ -855,6 +856,15 @@ static void tegra_pcie_enable_interrupts(struct dw_pcie_rp *pp)
tegra_pcie_enable_msi_interrupts(pp);
}
+static void tegra_pcie_disable_core_clk_m(struct tegra_pcie_dw *pcie)
+{
+ if (!pcie->core_clk_m_enabled)
+ return;
+
+ clk_disable_unprepare(pcie->core_clk_m);
+ pcie->core_clk_m_enabled = false;
+}
+
static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
{
struct dw_pcie *pci = &pcie->pci;
@@ -914,6 +924,7 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
u32 val;
u16 val_16;
+ int ret;
pp->bridge->ops = &tegra_pci_ops;
@@ -965,8 +976,12 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
}
clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
- if (clk_prepare_enable(pcie->core_clk_m))
- dev_err(pci->dev, "Failed to enable core monitor clock\n");
+ ret = clk_prepare_enable(pcie->core_clk_m);
+ if (ret) {
+ dev_err(pci->dev, "Failed to enable core monitor clock: %d\n", ret);
+ return ret;
+ }
+ pcie->core_clk_m_enabled = true;
return 0;
}
@@ -1049,8 +1064,11 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
* dw_pcie_host_init(). Disable the clock since below
* tegra_pcie_dw_host_init() will enable it again.
*/
- clk_disable_unprepare(pcie->core_clk_m);
- tegra_pcie_dw_host_init(pp);
+ tegra_pcie_disable_core_clk_m(pcie);
+ ret = tegra_pcie_dw_host_init(pp);
+ if (ret)
+ return ret;
+
dw_pcie_setup_rc(pp);
retry = false;
@@ -1565,6 +1583,7 @@ static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
return 0;
fail_host_init:
+ tegra_pcie_disable_core_clk_m(pcie);
tegra_pcie_unconfig_controller(pcie);
return ret;
}
@@ -1653,7 +1672,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
{
- clk_disable_unprepare(pcie->core_clk_m);
+ tegra_pcie_disable_core_clk_m(pcie);
dw_pcie_host_deinit(&pcie->pci.pp);
tegra_pcie_dw_pme_turnoff(pcie);
tegra_pcie_unconfig_controller(pcie);
@@ -2450,7 +2469,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)
if (!pcie->link_state)
return 0;
- clk_disable_unprepare(pcie->core_clk_m);
+ tegra_pcie_disable_core_clk_m(pcie);
tegra_pcie_dw_pme_turnoff(pcie);
tegra_pcie_unconfig_controller(pcie);
@@ -2487,6 +2506,7 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)
return 0;
fail_host_init:
+ tegra_pcie_disable_core_clk_m(pcie);
tegra_pcie_unconfig_controller(pcie);
return ret;
}
@@ -2528,6 +2548,7 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
if (IS_ENABLED(CONFIG_PCI_MSI))
disable_irq(pcie->pci.pp.msi_irq[0]);
+ tegra_pcie_disable_core_clk_m(pcie);
tegra_pcie_dw_pme_turnoff(pcie);
tegra_pcie_unconfig_controller(pcie);
pm_runtime_put_sync(pcie->dev);
--
2.34.1
next prev parent reply other threads:[~2026-09-23 7:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 7:22 [PATCH 00/11] PCI: tegra194: Fix EP and Root Port corner cases Manikanta Maddireddy
2026-09-23 7:22 ` [PATCH 01/11] PCI: tegra194: Propagate REFCLK select GPIO errors Manikanta Maddireddy
2026-09-23 7:22 ` [PATCH 02/11] PCI: tegra194: Check core reset deassertion Manikanta Maddireddy
2026-09-23 7:22 ` [PATCH 03/11] PCI: tegra194: Fix Endpoint PERST# IRQ suspend race Manikanta Maddireddy
2026-09-23 7:22 ` [PATCH 04/11] PCI: tegra194: Do not skip no-link Root Port remove cleanup Manikanta Maddireddy
2026-09-23 7:22 ` [PATCH 05/11] PCI: tegra194: Check for 16 GT/s capability before programming Manikanta Maddireddy
2026-09-23 7:22 ` [PATCH 06/11] PCI: tegra194: Check for L1SS " Manikanta Maddireddy
2026-09-23 7:22 ` [PATCH 07/11] PCI: tegra194: Always disable Tegra234 Endpoint L1.2 Manikanta Maddireddy
2026-09-23 7:22 ` [PATCH 08/11] PCI: tegra194: Guard Endpoint PLL-off error path Manikanta Maddireddy
2026-09-23 7:22 ` Manikanta Maddireddy [this message]
2026-09-23 7:22 ` [PATCH 10/11] PCI: tegra194: Fix Endpoint MSI/MSI-X numbering Manikanta Maddireddy
2026-09-23 13:32 ` Niklas Cassel
2026-09-23 7:22 ` [PATCH 11/11] PCI: endpoint: test: Do not relocate fixed MSI-X tables Manikanta Maddireddy
2026-09-23 14:32 ` Niklas Cassel
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