[PATCH 10/11] PCI: tegra194: Fix Endpoint MSI/MSI-X numbering

[Manikanta Maddireddy <mmaddireddy@nvidia.com>]

pci_epc_raise_irq() passes MSI and MSI-X interrupt numbers in the
1-N range. The Tegra MSI path rejected values above 32 but accepted
zero, which makes BIT(irq - 1) shift by a negative amount.

The Tegra MSI-X path also wrote that 1-based number to the DWC MSI-X
doorbell. The doorbell expects a zero-based vector index, matching the
common DesignWare doorbell helper which programs interrupt_num - 1.

Reject zero for both MSI and MSI-X, read the MSI-X table size directly
from the DWC capability, and write irq - 1 to the MSI-X doorbell.

Also advertise MSI-X support in the Tegra Endpoint features so endpoint
functions can expose and exercise the Tegra MSI-X path.

Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 25 ++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 9b337dbada70..513299541f18 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2026,7 +2026,7 @@ static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
 
 static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)
 {
-	if (unlikely(irq > 32))
+	if (unlikely(!irq || irq > 32))
 		return -EINVAL;
 
 	appl_writel(pcie, BIT(irq - 1), APPL_MSI_CTRL_1);
@@ -2034,11 +2034,26 @@ static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)
 	return 0;
 }
 
-static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq)
+static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie,
+					u8 func_no, u16 irq)
 {
 	struct dw_pcie_ep *ep = &pcie->pci.ep;
+	struct dw_pcie_ep_func *ep_func;
+	u32 reg;
+	u16 msix;
+	u16 val;
+
+	ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
+	if (!ep_func || !ep_func->msix_cap || !irq)
+		return -EINVAL;
+
+	reg = ep_func->msix_cap + PCI_MSIX_FLAGS;
+	val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
+	msix = FIELD_GET(PCI_MSIX_FLAGS_QSIZE, val) + 1;
+	if (!(val & PCI_MSIX_FLAGS_ENABLE) || irq > msix)
+		return -EINVAL;
 
-	writel(irq, ep->msi_mem);
+	writel(irq - 1, ep->msi_mem);
 
 	return 0;
 }
@@ -2057,7 +2072,8 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 		return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num);
 
 	case PCI_IRQ_MSIX:
-		return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num);
+		return tegra_pcie_ep_raise_msix_irq(pcie, func_no,
+						    interrupt_num);
 
 	default:
 		dev_err(pci->dev, "Unknown IRQ type\n");
@@ -2096,6 +2112,7 @@ static const struct pci_epc_features tegra_pcie_epc_features = {
 	DWC_EPC_COMMON_FEATURES,
 	.linkup_notifier = true,
 	.msi_capable = true,
+	.msix_capable = true,
 	.bar[BAR_0] = { .only_64bit = true, },
 	.bar[BAR_2] = {
 		.type = BAR_RESERVED,
-- 
2.34.1