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From: Niklas Cassel <cassel@kernel.org>
To: Manikanta Maddireddy <mmaddireddy@nvidia.com>,
	Koichiro Den <den@valinux.co.jp>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>,
	Krzysztof Wilczynski <kwilczynski@kernel.org>,
	Manivannan Sadhasivam <mani@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	linux-pci@vger.kernel.org, Rob Herring <robh@kernel.org>,
	Thierry Reding <thierry.reding@kernel.org>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	Frank Li <Frank.Li@kernel.org>, Vidya Sagar <vidyas@nvidia.com>,
	Marco Crivellari <marco.crivellari@suse.com>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 11/11] PCI: endpoint: test: Do not relocate fixed MSI-X tables
Date: Wed, 23 Sep 2026 16:32:33 +0200	[thread overview]
Message-ID: <arPjAeYzVbe5_qo8@ryzen> (raw)
In-Reply-To: <20260923072237.1139013-12-mmaddireddy@nvidia.com>

On Wed, Sep 23, 2026 at 12:52:37PM +0530, Manikanta Maddireddy wrote:
> Some endpoint controllers expose MSI-X table/PBA storage at fixed,
> hardware-owned BARs. Such BARs are described to endpoint functions as
> BAR_RESERVED with PCI_EPC_BAR_RSVD_MSIX_TBL_RAM, so the function driver
> must not reprogram the MSI-X Table/PBA capability to point into ordinary
> function BAR memory.
> 
> pci_epf_test always allocates MSI-X storage after its test registers and
> calls pci_epc_set_msix(). On controllers with fixed MSI-X storage, this
> overwrites the controller-defined MSI-X layout. For example, the generic
> DesignWare path derives the PBA offset from the number of vectors, which
> can make the host program the wrong MSI-X storage and prevent MSI-X
> delivery.
> 
> Detect fixed MSI-X table BARs and leave the controller-owned MSI-X
> capability layout unchanged. Keep allocating and programming MSI-X
> storage in the test BAR only for controllers that do not advertise fixed
> MSI-X table storage.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>  drivers/pci/endpoint/functions/pci-epf-test.c | 27 +++++++++++++++++--
>  1 file changed, 25 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
> index d4905aa8e4c0..82d4714e998c 100644
> --- a/drivers/pci/endpoint/functions/pci-epf-test.c
> +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
> @@ -83,6 +83,7 @@ struct pci_epf_test {
>  	struct config_group	group;
>  	enum pci_barno		test_reg_bar;
>  	size_t			msix_table_offset;
> +	bool			msix_table_fixed;
>  	struct delayed_work	cmd_handler;
>  	struct dma_chan		*dma_chan_tx;
>  	struct dma_chan		*dma_chan_rx;
> @@ -98,6 +99,26 @@ struct pci_epf_test {
>  	size_t			bar_size[PCI_STD_NUM_BARS];
>  };
>  
> +static bool pci_epf_test_msix_table_fixed(const struct pci_epc_features *features)
> +{
> +	enum pci_barno bar;
> +	int i;
> +
> +	for (bar = BAR_0; bar < PCI_STD_NUM_BARS; bar++) {
> +		const struct pci_epc_bar_desc *desc = &features->bar[bar];
> +
> +		if (desc->type != BAR_RESERVED)
> +			continue;
> +
> +		for (i = 0; i < desc->nr_rsvd_regions; i++) {
> +			if (desc->rsvd_regions[i].type == PCI_EPC_BAR_RSVD_MSIX_TBL_RAM)
> +				return true;
> +		}
> +	}
> +
> +	return false;
> +}
> +
>  struct pci_epf_test_reg {
>  	__le32 magic;
>  	__le32 command;
> @@ -1214,7 +1235,7 @@ static int pci_epf_test_epc_init(struct pci_epf *epf)
>  		}
>  	}
>  
> -	if (epc_features->msix_capable) {
> +	if (epc_features->msix_capable && !epf_test->msix_table_fixed) {
>  		ret = pci_epc_set_msix(epc, epf->func_no, epf->vfunc_no,
>  				       epf->msix_interrupts,
>  				       epf_test->test_reg_bar,
> @@ -1282,7 +1303,9 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
>  
>  	test_reg_bar_size = ALIGN(sizeof(struct pci_epf_test_reg), 128);
>  
> -	if (epc_features->msix_capable) {
> +	epf_test->msix_table_fixed = pci_epf_test_msix_table_fixed(epc_features);
> +
> +	if (epc_features->msix_capable && !epf_test->msix_table_fixed) {
>  		msix_table_size = PCI_MSIX_ENTRY_SIZE * epf->msix_interrupts;
>  		epf_test->msix_table_offset = test_reg_bar_size;
>  		/* Align to QWORD or 8 Bytes */

Here you are only updating pci-epf-test. What about the other EPF drivers?


Also, if you run then pci_endpoint kselftest, with the default 2048 MSI-X
interrupts. Are really all 2048 MSI-X successful?

It seems that often the "hardware owned" MSI-X table is much smaller than
that. See e.g. Koichiro's series which tries to use "hardware owned" MSI-X
table, but if the "hardware owned" MSI-X table is too small to hold all
2048 MSI-X IRQs, then "hardware owned" MSI-X table would not be used:

https://lore.kernel.org/linux-pci/20260830151948.3547577-2-den@valinux.co.jp/

+	if (layout->table_size < table_size || layout->pba_size < pba_size)
+		return -ENOSPC;



Apparently NTB EPF needs to read the MSI-X table from RAM:
https://lore.kernel.org/linux-pci/pj5vpwwd5tr5tuvhdq3bcpefnq27r6ljvwoysguz2o4tglcqx5@l7zmb6wjnhla/

Which is why he also decided to let an EPF driver choose if it should
use "hardware owned" MSI-X table or not.


Kind regards,
Niklas

      reply	other threads:[~2026-09-23 14:32 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-23  7:22 [PATCH 00/11] PCI: tegra194: Fix EP and Root Port corner cases Manikanta Maddireddy
2026-09-23  7:22 ` [PATCH 01/11] PCI: tegra194: Propagate REFCLK select GPIO errors Manikanta Maddireddy
2026-09-23  7:22 ` [PATCH 02/11] PCI: tegra194: Check core reset deassertion Manikanta Maddireddy
2026-09-24 20:25   ` Andy Shevchenko
2026-09-23  7:22 ` [PATCH 03/11] PCI: tegra194: Fix Endpoint PERST# IRQ suspend race Manikanta Maddireddy
2026-09-23  7:22 ` [PATCH 04/11] PCI: tegra194: Do not skip no-link Root Port remove cleanup Manikanta Maddireddy
2026-09-23  7:22 ` [PATCH 05/11] PCI: tegra194: Check for 16 GT/s capability before programming Manikanta Maddireddy
2026-09-23  7:22 ` [PATCH 06/11] PCI: tegra194: Check for L1SS " Manikanta Maddireddy
2026-09-23  7:22 ` [PATCH 07/11] PCI: tegra194: Always disable Tegra234 Endpoint L1.2 Manikanta Maddireddy
2026-09-23  7:22 ` [PATCH 08/11] PCI: tegra194: Guard Endpoint PLL-off error path Manikanta Maddireddy
2026-09-23  7:22 ` [PATCH 09/11] PCI: tegra194: Balance core monitor clock on failures Manikanta Maddireddy
2026-09-23  7:22 ` [PATCH 10/11] PCI: tegra194: Fix Endpoint MSI/MSI-X numbering Manikanta Maddireddy
2026-09-23 13:32   ` Niklas Cassel
2026-09-23  7:22 ` [PATCH 11/11] PCI: endpoint: test: Do not relocate fixed MSI-X tables Manikanta Maddireddy
2026-09-23 14:32   ` Niklas Cassel [this message]

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