From: Vishal Badole <Vishal.Badole@amd.com>
To: <bp@alien8.de>, <yazen.ghannam@amd.com>, <tony.luck@intel.com>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Vishal Badole <Vishal.Badole@amd.com>
Subject: [PATCH Intenal 0/2] EDAC/amd64: Add Family 1Ah Model 80h-8Fh support and fix csrow decode
Date: Wed, 23 Sep 2026 16:50:01 +0530 [thread overview]
Message-ID: <20260923112003.3677719-1-Vishal.Badole@amd.com> (raw)
This series adds AMD Family 1Ah Model 80h-8Fh support to the amd64_edac
driver and fixes a UMC csrow decode issue seen on that part.
Patch 1 adds support for Family 1Ah Model 80h-8Fh.
Patch 2 fixes the chip select decode for DRAM ECC errors. The syndrome
field was masked assuming eight chip selects while the controller
implements four, producing an out-of-range csrow and an error reported
against "unknown memory". Mask with the number of chip selects the
controller actually implements.
Tested on a Family 1Ah Model 88h board with injected ECC errors.
Vishal Badole (2):
EDAC/amd64: Add support for AMD family 1Ah models 80h-8Fh
EDAC/amd64: Limit UMC csrow decode to the implemented chip selects
drivers/edac/amd64_edac.c | 17 +++++++++++------
drivers/edac/amd64_edac.h | 2 +-
2 files changed, 12 insertions(+), 7 deletions(-)
--
2.34.1
next reply other threads:[~2026-09-23 11:20 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 11:20 Vishal Badole [this message]
2026-09-23 11:20 ` [PATCH Intenal 1/2] EDAC/amd64: Add support for AMD family 1Ah models 80h-8Fh Vishal Badole
2026-09-24 14:11 ` Yazen Ghannam
2026-09-23 11:20 ` [PATCH Intenal 2/2] EDAC/amd64: Limit UMC csrow decode to the implemented chip selects Vishal Badole
2026-09-24 14:27 ` Yazen Ghannam
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