From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Vishal Badole <Vishal.Badole@amd.com>
Cc: bp@alien8.de, tony.luck@intel.com, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH Intenal 1/2] EDAC/amd64: Add support for AMD family 1Ah models 80h-8Fh
Date: Thu, 24 Sep 2026 10:11:46 -0400 [thread overview]
Message-ID: <20260924141146.GD1080284@yaz-khff2.amd.com> (raw)
In-Reply-To: <20260923112003.3677719-2-Vishal.Badole@amd.com>
On Wed, Sep 23, 2026 at 04:50:02PM +0530, Vishal Badole wrote:
> Add support for family 1Ah-based models 80h-8Fh.
>
> Signed-off-by: Vishal Badole <Vishal.Badole@amd.com>
> ---
> drivers/edac/amd64_edac.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index c6aa69dbd9fb..ff0ebc8e15f6 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -3900,6 +3900,10 @@ static int per_family_init(struct amd64_pvt *pvt)
> pvt->max_mcs = 16;
> pvt->flags.zn_regs_v2 = 1;
> break;
> + case 0x80 ... 0x8f:
> + pvt->max_mcs = 2;
Should this be '4'?
In documentation, I see 4 UMC MCA banks, and the UMC register
definitions list UMC0-UMC3 instances.
Thanks,
Yazen
next prev parent reply other threads:[~2026-09-24 14:11 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 11:20 [PATCH Intenal 0/2] EDAC/amd64: Add Family 1Ah Model 80h-8Fh support and fix csrow decode Vishal Badole
2026-09-23 11:20 ` [PATCH Intenal 1/2] EDAC/amd64: Add support for AMD family 1Ah models 80h-8Fh Vishal Badole
2026-09-24 14:11 ` Yazen Ghannam [this message]
2026-09-23 11:20 ` [PATCH Intenal 2/2] EDAC/amd64: Limit UMC csrow decode to the implemented chip selects Vishal Badole
2026-09-24 14:27 ` Yazen Ghannam
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