From: Jason Gunthorpe <jgg@nvidia.com>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: will@kernel.org, robin.murphy@arm.com,
Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>,
joro@8bytes.org, bhelgaas@google.com, praan@google.com,
kevin.tian@intel.com, kees@kernel.org, smostafa@google.com,
baolu.lu@linux.intel.com, Jean-Philippe Brucker <jpb@kernel.org>,
Eric Auger <eric.auger@redhat.com>,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
skaestle@nvidia.com, mmarrid@nvidia.com, skolothumtho@nvidia.com,
bbiber@nvidia.com, harsha.v@oss.qualcomm.com
Subject: Re: [PATCH v5 04/15] iommu/arm-smmu-v3: Drain in-flight fault events on domain detach
Date: Wed, 23 Sep 2026 20:39:20 -0300 [thread overview]
Message-ID: <20260923233920.GJ2545495@nvidia.com> (raw)
In-Reply-To: <arRTojIlWBOF57zO@nvidia.com>
On Wed, Sep 23, 2026 at 03:33:06PM -0700, Nicolin Chen wrote:
> > I'm not sure how this all can work, the queue is running on its own
> > with some other CPU handling interrupts.
> >
> > You can't do this sort of Q_DIFF math unless you've somehow guaranteed
> > one side of the queue is stable for this logic. If both pointers are
> > moving forward then the points pointers can progress and wrap without
> > this noticing that happened. That will lock up.
>
> One side of the queue (pointers) is actually stable. EVTQ/PRIQ uses
> the snapshot mode (until_empty=false):
It isn't stable, just because this reads it once doesn't mean the
actual values are not changing, which is the point.
If one of the pointers is held stable then the HW cannot advance its
value past it.
If both are advancing all bets are off and you have no idea how the
values are related to each other since everything is modulo the ring
size.
For instance you can read cons0=10, then you read prod=15, then you
next read prod=11. What does that mean? It means since cons was
actually advancing prod & cons went around the whole ring and
wrapped.
You could only do tricks like this if you had full 64 bit counters,
not truncated versions with modulo that can wrap quickly.
> > But I wonder if the point of this has been lost? Prior to calling the
> > driver attach functions the core code already changes the xarray:
> >
> > curr = xa_cmpxchg(&group->pasid_array, pasid, NULL,
> > XA_ZERO_ENTRY, GFP_KERNEL);
> >
> > That immediately makes the threaded IRQ safe since it calls
> > iommu_attach_handle_get() which now fails.
Hmm, actually that's a sneaky cmpxchg that is only doing reserve..
> I am not sure about that. Looking at iommufd_hwpt_replace_device(),
> there can be a old_handle != NULL, in which case the cmpxchg() would
> not change the xarray?
I think this is wrong, there is no way it can work like this where the
attach continues to see the to-be-detached domain across the
flushes. No amount of flushing can fix it.
Somehow we broke it :\
> > So all that is needed is to synchronize_irq() to make sure the irq
> > thread sees the xa update
> >
> > Then to flush the workqueue that iommu_report_device_fault() pushes
> > into.
> >
> > We don't need to do anything with the HW queue.
>
> FWIW, the idea of HW drain came from intel_iommu_drain_pasid_prq()..
Yeah, but I think they might have over done it too..
Jason
next prev parent reply other threads:[~2026-09-23 23:39 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 16:38 [PATCH v5 00/15] iommu/arm-smmu-v3: Add PRI support Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 01/15] iommu/arm-smmu-v3: Disable the impl before disabling the SMMU on shutdown Nicolin Chen
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-15 16:38 ` [PATCH v5 02/15] iommu/arm-smmu-v3: Add arm_smmu_attach_release() Nicolin Chen
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-15 16:38 ` [PATCH v5 03/15] iommu/arm-smmu-v3: Add Q_POS() macro Nicolin Chen
2026-09-15 23:19 ` Jonathan Cameron
2026-09-15 16:38 ` [PATCH v5 04/15] iommu/arm-smmu-v3: Drain in-flight fault events on domain detach Nicolin Chen
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-23 22:33 ` Nicolin Chen
2026-09-23 23:39 ` Jason Gunthorpe [this message]
2026-09-24 1:42 ` Nicolin Chen
2026-09-24 14:03 ` Jason Gunthorpe
2026-09-15 16:38 ` [PATCH v5 05/15] iommu/arm-smmu-v3: Flush in-flight fault work " Nicolin Chen
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-15 16:38 ` [PATCH v5 06/15] iommu/arm-smmu-v3: Allocate IOPF queue without FEAT_SVA Nicolin Chen
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-15 16:38 ` [PATCH v5 07/15] iommu/arm-smmu-v3: Submit CMDQ_OP_PRI_RESP for IOPF event Nicolin Chen
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-15 16:38 ` [PATCH v5 08/15] iommu/arm-smmu-v3: Disable the queue IRQs before disabling the SMMU Nicolin Chen
2026-09-15 23:21 ` Jonathan Cameron
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-24 1:12 ` Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 09/15] iommu/arm-smmu-v3: Disable PRI when no IRQ handler is registered Nicolin Chen
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-15 16:38 ` [PATCH v5 10/15] iommu/arm-smmu-v3: Support PRI Page Request in arm_smmu_handle_ppr() Nicolin Chen
2026-09-15 23:22 ` Jonathan Cameron
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-15 16:38 ` [PATCH v5 11/15] iommu/arm-smmu-v3: Discard partial PRI faults on PRIQ overflow Nicolin Chen
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-15 16:38 ` [PATCH v5 12/15] iommu/arm-smmu-v3: Allocate IOPF queue for ARM_SMMU_FEAT_PRI Nicolin Chen
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-15 16:38 ` [PATCH v5 13/15] PCI/ATS: Add PRI stubs Nicolin Chen
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-15 16:38 ` [PATCH v5 14/15] PCI/ATS: Export pci_enable_pri() and pci_reset_pri() Nicolin Chen
2026-09-23 18:37 ` Jason Gunthorpe
2026-09-15 16:38 ` [PATCH v5 15/15] iommu/arm-smmu-v3: Enable PRI for PCI device in arm_smmu_probe_device() Nicolin Chen
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