[PATCH 0/2] EDAC/amd64: Consolidate Family 1Ah setup and fix UMC csrow decode

[PATCH 0/2] EDAC/amd64: Consolidate Family 1Ah setup and fix UMC csrow decode

[Vishal Badole]

Two small amd64_edac cleanups/fixes for AMD Family 1Ah.

Patch 1 sets zn_regs_v2 once at the Family 1Ah level instead of in each
model case, so future models cannot miss the v2 register layout. No
functional change.

Patch 2 masks the UMC chip select from MCA_SYND with 0x3 instead of 0x7.
Only four chip selects are ever implemented, so the old mask could decode
an out-of-range csrow and trip an EDAC core warning.

Vishal Badole (2):
  EDAC/amd64: Set zn_regs_v2 for all Family 1Ah models
  EDAC/amd64: Mask UMC chip select to the four implemented selects

 drivers/edac/amd64_edac.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

-- 
2.34.1

[PATCH 1/2] EDAC/amd64: Set zn_regs_v2 for all Family 1Ah models

[Vishal Badole]

The v2 register layout applies to every Family 1Ah model, but
zn_regs_v2 is set individually in each model case of the switch. All
currently supported models set it, so this is not a live bug; however a
model added later without its own case, or in a case that omits the
assignment, would read the UMC registers at the wrong offsets.

Set zn_regs_v2 once at the Family 1Ah level so it applies to all models
uniformly, and drop the per-model assignments.

No functional change intended.

Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Vishal Badole <Vishal.Badole@amd.com>
---
 drivers/edac/amd64_edac.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 475235c402e8..cab696be4f07 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3887,23 +3887,19 @@ static int per_family_init(struct amd64_pvt *pvt)
 		break;
 
 	case 0x1A:
+		pvt->flags.zn_regs_v2   = 1;
+
 		switch (pvt->model) {
 		case 0x00 ... 0x1f:
 			pvt->max_mcs            = 12;
-			pvt->flags.zn_regs_v2   = 1;
-			break;
-		case 0x40 ... 0x4f:
-			pvt->flags.zn_regs_v2   = 1;
 			break;
 		case 0x50 ... 0x57:
 		case 0xc0 ... 0xc7:
 			pvt->max_mcs            = 16;
-			pvt->flags.zn_regs_v2   = 1;
 			break;
 		case 0x90 ... 0x9f:
 		case 0xa0 ... 0xaf:
 			pvt->max_mcs            = 8;
-			pvt->flags.zn_regs_v2   = 1;
 			break;
 		}
 		break;
-- 
2.34.1

[PATCH 2/2] EDAC/amd64: Mask UMC chip select to the four implemented selects

[Vishal Badole]

umc_get_err_info() masks the Chip Select from MCA_SYND with 0x7, a
leftover from Zen 1 where the architecture reserved space for up to
eight chip selects. Only four have ever been implemented, and newer
products document this as MCA_SYND_UMC[1:0] = Chip Select.

Since only four csrows are allocated, a syndrome with bit 2 set decodes
to an out-of-range csrow and trips:

  EDAC MC0: INTERNAL ERROR: csrow value is out of range (5 >= 4)

Mask with 0x3 to match the four implemented chip selects.

Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Vishal Badole <Vishal.Badole@amd.com>
---
 drivers/edac/amd64_edac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index cab696be4f07..b69c3f51dd37 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2802,7 +2802,7 @@ static inline void decode_bus_error(int node_id, struct mce *m)
 static void umc_get_err_info(struct mce *m, struct err_info *err)
 {
 	err->channel = (m->ipid & GENMASK(31, 0)) >> 20;
-	err->csrow = m->synd & 0x7;
+	err->csrow = m->synd & 0x3;
 }
 
 static void decode_umc_error(int node_id, struct mce *m)
-- 
2.34.1

Re: [PATCH 2/2] EDAC/amd64: Mask UMC chip select to the four implemented selects

[Borislav Petkov]

On Fri, Sep 25, 2026 at 10:56:39PM +0530, Vishal Badole wrote:
> umc_get_err_info() masks the Chip Select from MCA_SYND with 0x7, a
> leftover from Zen 1 where the architecture reserved space for up to
> eight chip selects. Only four have ever been implemented, and newer
> products document this as MCA_SYND_UMC[1:0] = Chip Select.
> 
> Since only four csrows are allocated, a syndrome with bit 2 set decodes
> to an out-of-range csrow and trips:
> 
>   EDAC MC0: INTERNAL ERROR: csrow value is out of range (5 >= 4)
> 
> Mask with 0x3 to match the four implemented chip selects.
> 
> Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
> Signed-off-by: Vishal Badole <Vishal.Badole@amd.com>
> ---
>  drivers/edac/amd64_edac.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index cab696be4f07..b69c3f51dd37 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -2802,7 +2802,7 @@ static inline void decode_bus_error(int node_id, struct mce *m)
>  static void umc_get_err_info(struct mce *m, struct err_info *err)
>  {
>  	err->channel = (m->ipid & GENMASK(31, 0)) >> 20;
> -	err->csrow = m->synd & 0x7;
> +	err->csrow = m->synd & 0x3;
>  }
>  
>  static void decode_umc_error(int node_id, struct mce *m)
> -- 

Is this ever going to change?

Do we need to track this in the per-model struct, i.e., what your patch 1 is
touching?

Is this a fix that needs to go to stable? If so, Fixes: tag and CC:stable.

If so, patches going to stable go first and need to be minimal for ease of
backporting.

Thx.

-- 
Regards/Gruss,
    Boris.

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