From: David Zhang <yidong.zhang@amd.com>
To: <quic_jhugo@quicinc.com>, <karol.wachowski@linux.intel.com>,
<max.zhen@amd.com>, <lizhi.hou@amd.com>, <ogabbay@kernel.org>,
<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>
Cc: David Zhang <yidong.zhang@amd.com>, <sonal.santan@amd.com>,
<mario.limonciello@amd.com>, Nishad Saraf <nishads@amd.com>
Subject: [PATCH V0 10/21] accel/amdxdna: Add context switch hysteresis with debugfs control
Date: Fri, 25 Sep 2026 18:34:37 -0700 [thread overview]
Message-ID: <20260926013448.3840921-11-yidong.zhang@amd.com> (raw)
In-Reply-To: <20260926013448.3840921-1-yidong.zhang@amd.com>
Add aie4_set_ctx_hysteresis() to configure the AIE4 context switch
hysteresis timeout via the SET_RUNTIME_CONFIG message, applied at hw
start (PF and classic paths) with a default of 1000 us.
Expose a debugfs node 'ctx_switch_hysteresis_us' to change the timeout
at runtime (0 disables hysteresis). The stored value is re-applied on
every hw start so it survives runtime suspend/resume.
Co-developed-by: Nishad Saraf <nishads@amd.com>
Signed-off-by: Nishad Saraf <nishads@amd.com>
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_message.c | 50 +++++++++++++++
drivers/accel/amdxdna/aie4_msg_priv.h | 36 +++++++++++
drivers/accel/amdxdna/aie4_pci.c | 85 ++++++++++++++++++++++++-
drivers/accel/amdxdna/aie4_pci.h | 12 ++++
drivers/accel/amdxdna/amdxdna_debugfs.c | 3 +
drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 +
6 files changed, 185 insertions(+), 2 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
index 6d1f1561638b..ff776f478733 100644
--- a/drivers/accel/amdxdna/aie4_message.c
+++ b/drivers/accel/amdxdna/aie4_message.c
@@ -247,3 +247,53 @@ int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode)
return ret;
}
+
+int aie4_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type,
+ const void *data, size_t size)
+{
+ DECLARE_AIE_MSG(aie4_msg_set_runtime_cfg, AIE4_MSG_OP_SET_RUNTIME_CONFIG);
+ u8 buf[sizeof(req.type) + AIE4_RUNTIME_CFG_MAX_DATA_SIZE] = { 0 };
+ int ret;
+
+ if (size > AIE4_RUNTIME_CFG_MAX_DATA_SIZE)
+ return -EINVAL;
+
+ /*
+ * Firmware expects a 4-byte @type immediately followed by the
+ * per-type payload (size validated against the struct npu_msg_-
+ * runtime_config_* picked by @type). The shared request struct
+ * carries an inline @data[4] slot, so stage only the 4-byte @type
+ * header plus the variable payload contiguously and send exactly
+ * that many bytes on the wire.
+ */
+ req.type = type;
+ memcpy(buf, &req.type, sizeof(req.type));
+ memcpy(buf + sizeof(req.type), data, size);
+
+ msg.send_data = buf;
+ msg.send_size = sizeof(req.type) + size;
+
+ ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg);
+ if (ret)
+ XDNA_ERR(ndev->aie.xdna, "Failed to set runtime cfg %u: %d", type, ret);
+ return ret;
+}
+
+int aie4_set_ctx_hysteresis(struct amdxdna_dev_hdl *ndev, u32 timeout_us)
+{
+ struct aie4_msg_runtime_config_ctx_switch_hysteresis cfg = {
+ .timeout_us = timeout_us,
+ };
+ int ret;
+
+ ret = aie4_set_runtime_cfg(ndev, AIE4_RUNTIME_CONFIG_CTX_SWITCH_HYSTERESIS,
+ &cfg, sizeof(cfg));
+ if (ret)
+ XDNA_WARN(ndev->aie.xdna,
+ "Failed to set ctx switch hysteresis to %u us (%d), using fw default",
+ timeout_us, ret);
+ else
+ XDNA_DBG(ndev->aie.xdna, "Context switch hysteresis set to %u us", timeout_us);
+
+ return ret;
+}
diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
index fe78df9e23c8..77984683a7b6 100644
--- a/drivers/accel/amdxdna/aie4_msg_priv.h
+++ b/drivers/accel/amdxdna/aie4_msg_priv.h
@@ -12,6 +12,7 @@
enum aie4_msg_opcode {
AIE4_MSG_OP_IDENTIFY = 0x10002,
AIE4_MSG_OP_SUSPEND = 0x10003,
+ AIE4_MSG_OP_SET_RUNTIME_CONFIG = 0x10007,
AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION = 0x1000F,
AIE4_MSG_OP_CREATE_VFS = 0x20001,
@@ -65,6 +66,41 @@ struct aie4_msg_suspend_resp {
enum aie4_msg_status status;
} __packed;
+/*
+ * Type selector for AIE4_MSG_OP_SET_RUNTIME_CONFIG. Values match the firmware
+ * ABI enum npu_msg_runtime_config_type; only the configs the driver programs
+ * are enumerated here.
+ */
+enum aie4_msg_runtime_config_type {
+ AIE4_RUNTIME_CONFIG_CTX_SWITCH_HYSTERESIS = 0xD,
+ AIE4_MAX_RUNTIME_CONFIG
+};
+
+struct aie4_msg_set_runtime_cfg_req {
+ __u32 type;
+ __u8 data[4];
+} __packed;
+
+struct aie4_msg_set_runtime_cfg_resp {
+ enum aie4_msg_status status;
+} __packed;
+
+/* Maximum trailing per-type payload (struct npu_msg_runtime_config_*) in the
+ * firmware ABI; today the largest is npu_msg_runtime_config_event_trace_status
+ * at 12 bytes. Rounded up to leave headroom for future configs.
+ */
+#define AIE4_RUNTIME_CFG_MAX_DATA_SIZE 16
+
+/*
+ * Context switch hysteresis configuration.
+ *
+ * @timeout_us: Hysteresis time in microseconds for keeping a context loaded
+ * in the AIE after it becomes idle, or 0 to disable hysteresis.
+ */
+struct aie4_msg_runtime_config_ctx_switch_hysteresis {
+ __u32 timeout_us;
+} __packed;
+
struct aie4_msg_create_vfs_req {
__u32 vf_cnt;
} __packed;
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index 05c181626173..e1484d384d3d 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -5,8 +5,10 @@
#include <drm/amdxdna_accel.h>
#include <drm/drm_drv.h>
+#include <drm/drm_file.h>
#include <drm/drm_managed.h>
#include <drm/drm_print.h>
+#include <linux/debugfs.h>
#include <linux/firmware.h>
#include <linux/sizes.h>
@@ -325,6 +327,20 @@ int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev)
return aie4_msg_set_power_mode(ndev, ndev->pw_mode);
}
+static int aie4_config_fw(struct amdxdna_dev_hdl *ndev)
+{
+ int ret;
+
+ ret = aie4_attach_work_buffer(ndev);
+ if (ret)
+ return ret;
+
+ /* Best-effort tuning knob; failure is warned inside and does not fail hw start */
+ aie4_set_ctx_hysteresis(ndev, ndev->ctx_switch_hysteresis_us);
+
+ return 0;
+}
+
static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
{
int ret;
@@ -337,7 +353,7 @@ static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev)
if (ret)
goto stop_fw;
- ret = aie4_attach_work_buffer(ndev);
+ ret = aie4_config_fw(ndev);
if (ret)
goto mbox_fini;
@@ -419,7 +435,7 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
if (ret)
goto mailbox_fini;
- ret = aie4_attach_work_buffer(ndev);
+ ret = aie4_config_fw(ndev);
if (ret)
goto mailbox_fini;
@@ -574,6 +590,7 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna)
ndev->priv = xdna->dev_info->dev_priv;
ndev->aie.xdna = xdna;
+ ndev->ctx_switch_hysteresis_us = AIE4_CTX_HYSTERESIS_US;
ndev->pw_mode = POWER_MODE_DEFAULT;
xdna->dev_handle = ndev;
@@ -920,15 +937,78 @@ static void aie4_classic_fini(struct amdxdna_dev *xdna)
aie4_free_work_buffer(xdna->dev_handle);
}
+static int aie4_ctx_hysteresis_get(void *data, u64 *val)
+{
+ struct amdxdna_dev_hdl *ndev = data;
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+
+ guard(mutex)(&xdna->dev_lock);
+ *val = ndev->ctx_switch_hysteresis_us;
+
+ return 0;
+}
+
+static int aie4_ctx_hysteresis_set(void *data, u64 val)
+{
+ struct amdxdna_dev_hdl *ndev = data;
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+ int ret, idx;
+
+ if (val > U32_MAX)
+ return -EINVAL;
+
+ if (!drm_dev_enter(&xdna->ddev, &idx))
+ return -ENODEV;
+
+ mutex_lock(&xdna->dev_lock);
+
+ ret = amdxdna_pm_resume_get_locked(xdna);
+ if (ret)
+ goto unlock;
+
+ ret = aie4_set_ctx_hysteresis(ndev, (u32)val);
+ if (!ret)
+ ndev->ctx_switch_hysteresis_us = (u32)val;
+
+ amdxdna_pm_suspend_put(xdna);
+
+unlock:
+ mutex_unlock(&xdna->dev_lock);
+ drm_dev_exit(idx);
+
+ return ret;
+}
+
+/* Context switch hysteresis timeout in microseconds; 0 disables hysteresis. */
+DEFINE_DEBUGFS_ATTRIBUTE(aie4_ctx_hysteresis_fops, aie4_ctx_hysteresis_get,
+ aie4_ctx_hysteresis_set, "%llu\n");
+
+static void aie4_debugfs_init(struct amdxdna_dev *xdna)
+{
+ struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+
+ /*
+ * Context switch hysteresis is a system-control runtime config that is
+ * only programmed on the PF/classic hw start paths, never on a VF.
+ * Only expose the knob where the driver actually applies it.
+ */
+ if (!to_pci_dev(xdna->ddev.dev)->is_virtfn)
+ debugfs_create_file_unsafe("ctx_switch_hysteresis_us", 0600,
+ xdna->ddev.accel->debugfs_root, ndev,
+ &aie4_ctx_hysteresis_fops);
+}
+
const struct amdxdna_dev_ops aie4_pf_ops = {
.init = aie4_pf_init,
.fini = aie4_pf_fini,
+ .debugfs_init = aie4_debugfs_init,
.sriov_configure = aie4_sriov_configure,
};
const struct amdxdna_dev_ops aie4_vf_ops = {
.init = aie4_vf_init,
.fini = aie4_vf_fini,
+ .debugfs_init = aie4_debugfs_init,
.hwctx_init = aie4_hwctx_init,
.hwctx_fini = aie4_hwctx_fini,
.cmd_wait = aie4_cmd_wait,
@@ -939,6 +1019,7 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
const struct amdxdna_dev_ops aie4_classic_ops = {
.init = aie4_classic_init,
.fini = aie4_classic_fini,
+ .debugfs_init = aie4_debugfs_init,
.hwctx_init = aie4_hwctx_init,
.hwctx_fini = aie4_hwctx_fini,
.cmd_wait = aie4_cmd_wait,
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index 6e9e7f874a44..063cedfe3c9d 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -14,6 +14,9 @@
#include "aie4_msg_priv.h"
#include "amdxdna_mailbox.h"
+/* Default context switch hysteresis timeout in microseconds. */
+#define AIE4_CTX_HYSTERESIS_US 1000
+
struct cert_comp {
struct amdxdna_dev_hdl *ndev;
u32 msix_idx;
@@ -69,6 +72,12 @@ struct amdxdna_dev_hdl {
u8 pw_mode;
+ /*
+ * Context switch hysteresis timeout in microseconds; pushed to the
+ * firmware at hw start and tunable at runtime via debugfs.
+ */
+ u32 ctx_switch_hysteresis_us;
+
struct amdxdna_drm_query_firmware_version cert_version;
};
@@ -92,6 +101,9 @@ int aie4_init_dpm_freq_table(struct amdxdna_dev_hdl *ndev);
int aie4_query_dpm_level(struct amdxdna_dev_hdl *ndev,
u32 *aieclk_dpm_level, u32 *npuhclk_dpm_level);
int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode);
+int aie4_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type,
+ const void *data, size_t size);
+int aie4_set_ctx_hysteresis(struct amdxdna_dev_hdl *ndev, u32 timeout_us);
u32 aie4_msg_pasid(struct amdxdna_client *client);
/* aie4_ctx.c */
diff --git a/drivers/accel/amdxdna/amdxdna_debugfs.c b/drivers/accel/amdxdna/amdxdna_debugfs.c
index a6ec17c63629..1f63cc91b168 100644
--- a/drivers/accel/amdxdna/amdxdna_debugfs.c
+++ b/drivers/accel/amdxdna/amdxdna_debugfs.c
@@ -126,4 +126,7 @@ void amdxdna_debugfs_init(struct amdxdna_dev *xdna)
xdna,
amdxdna_dbgfs_files[i].fops);
}
+
+ if (xdna->dev_info->ops->debugfs_init)
+ xdna->dev_info->ops->debugfs_init(xdna);
}
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
index 953bf783b3f7..11f46ec738d7 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
@@ -54,6 +54,7 @@ struct amdxdna_sched_job;
struct amdxdna_dev_ops {
int (*init)(struct amdxdna_dev *xdna);
void (*fini)(struct amdxdna_dev *xdna);
+ void (*debugfs_init)(struct amdxdna_dev *xdna);
int (*resume)(struct amdxdna_dev *xdna);
int (*suspend)(struct amdxdna_dev *xdna);
int (*sriov_configure)(struct amdxdna_dev *xdna, int num_vfs);
--
2.34.1
next prev parent reply other threads:[~2026-09-26 1:35 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-26 1:34 [PATCH V0 00/21] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
2026-09-26 1:34 ` [PATCH V0 01/21] accel/amdxdna: Rename NPU3 firmware files David Zhang
2026-09-26 1:34 ` [PATCH V0 02/21] accel/amdxdna: Remove mmap for doorbell David Zhang
2026-09-26 1:34 ` [PATCH V0 03/21] accel/amdxdna: Add CERT firmware version support David Zhang
2026-09-26 1:34 ` [PATCH V0 04/21] accel/amdxdna: Upgrade firmware version to 6.0 David Zhang
2026-09-28 17:08 ` Lizhi Hou
2026-09-26 1:34 ` [PATCH V0 05/21] accel/amdxdna: Add NPU3 classic device support David Zhang
2026-09-26 1:34 ` [PATCH V0 06/21] accel/amdxdna: Add AIE version query to aie4_get_info David Zhang
2026-09-26 1:34 ` [PATCH V0 07/21] accel/amdxdna: Add get and set power_mode for AIE4 David Zhang
2026-09-28 18:39 ` Lizhi Hou
2026-09-26 1:34 ` [PATCH V0 08/21] accel/amdxdna: Restore power mode override on AIE4 hardware start David Zhang
2026-09-28 18:48 ` Lizhi Hou
2026-09-26 1:34 ` [PATCH V0 09/21] accel/amdxdna: Add clock, DPM frequency, and resource info queries for AIE4 David Zhang
2026-09-26 1:34 ` David Zhang [this message]
2026-09-26 1:34 ` [PATCH V0 11/21] accel/amdxdna: Refactor AIE4 hardware initialization sequence David Zhang
2026-09-26 1:34 ` [PATCH V0 12/21] accel/amdxdna: Decouple AIE4 doorbell and MSI-X notification transport hooks David Zhang
2026-09-28 20:16 ` Lizhi Hou
2026-09-26 1:34 ` [PATCH V0 13/21] accel/amdxdna: Implement AIE4 kernel queue lifecycle and memory layout David Zhang
2026-09-26 1:34 ` [PATCH V0 14/21] accel/amdxdna: Fix fence timeline name and context allocation David Zhang
2026-09-28 21:06 ` Lizhi Hou
2026-09-30 0:20 ` Zhang, Yidong (David)
2026-09-26 1:34 ` [PATCH V0 15/21] accel/amdxdna: Prepare for AIE4 command submission David Zhang
2026-09-26 1:34 ` [PATCH V0 16/21] accel/amdxdna: Implement AIE4 command packet building and submission David Zhang
2026-09-26 1:34 ` [PATCH V0 17/21] accel/amdxdna: Finalize runtime PM before acquiring dev_lock on removal David Zhang
2026-09-26 1:34 ` [PATCH V0 18/21] accel/amdxdna: Implement AIE4 suspend and resume David Zhang
2026-09-26 1:34 ` [PATCH V0 19/21] accel/amdxdna: Link SR-IOV VFs for power management sequencing David Zhang
2026-09-26 1:34 ` [PATCH V0 20/21] accel/amdxdna: Implement runtime suspend and resume support David Zhang
2026-09-26 1:34 ` [PATCH V0 21/21] accel/amdxdna: Add stub hwctx_config for AIE4 David Zhang
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