From: Lizhi Hou <lizhi.hou@amd.com>
To: David Zhang <yidong.zhang@amd.com>, <quic_jhugo@quicinc.com>,
<karol.wachowski@linux.intel.com>, <max.zhen@amd.com>,
<ogabbay@kernel.org>, <dri-devel@lists.freedesktop.org>,
<linux-kernel@vger.kernel.org>
Cc: <sonal.santan@amd.com>, <mario.limonciello@amd.com>
Subject: Re: [PATCH V0 04/21] accel/amdxdna: Upgrade firmware version to 6.0
Date: Mon, 28 Sep 2026 10:08:35 -0700 [thread overview]
Message-ID: <d65c9328-04f7-2f06-1265-4a5d7f3a8698@amd.com> (raw)
In-Reply-To: <20260926013448.3840921-5-yidong.zhang@amd.com>
On 9/25/26 18:34, David Zhang wrote:
> Upgrade firmware interface version to 6.0. Update host queue layout,
> opcode definitions, and context creation/destruction request structures.
> Parse priority band and PASID for hardware context creation.
>
> Note on host queue layout and version validation:
> The host queue header layout moves write_index from offset 16 to offset 64
> and data_address from offset 24 to offset 120. Protocol compatibility for
> this queue layout is validated against the CERT firmware protocol version
> (host_queue_major/minor via aie_check_cert_protocol()), which was
> introduced in the preceding patch ("accel/amdxdna: Add CERT firmware
> version support").
>
> Signed-off-by: David Zhang <yidong.zhang@amd.com>
> ---
> drivers/accel/amdxdna/aie4_ctx.c | 21 ++++++++++++++++++---
> drivers/accel/amdxdna/aie4_host_queue.h | 14 ++++++++++++--
> drivers/accel/amdxdna/aie4_message.c | 10 ++++++++++
> drivers/accel/amdxdna/aie4_msg_priv.h | 20 +++++++++++++++++---
> drivers/accel/amdxdna/aie4_pci.h | 1 +
> drivers/accel/amdxdna/npu3_regs.c | 2 +-
> 6 files changed, 59 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
> index 8157f2a6fd10..90da4e8c4f54 100644
> --- a/drivers/accel/amdxdna/aie4_ctx.c
> +++ b/drivers/accel/amdxdna/aie4_ctx.c
> @@ -110,6 +110,22 @@ static int aie4_msg_destroy_context(struct amdxdna_dev_hdl *ndev, u32 hw_context
> return aie_send_mgmt_msg_wait(&ndev->aie, &msg);
> }
>
> +static u8 aie4_parse_priority_to_dev(u32 priority)
> +{
> + switch (priority) {
> + case AMDXDNA_QOS_LOW_PRIORITY:
> + return AIE4_CONTEXT_PRIORITY_BAND_IDLE;
> + case AMDXDNA_QOS_NORMAL_PRIORITY:
> + return AIE4_CONTEXT_PRIORITY_BAND_NORMAL;
> + case AMDXDNA_QOS_HIGH_PRIORITY:
> + return AIE4_CONTEXT_PRIORITY_BAND_FOCUS;
> + case AMDXDNA_QOS_REALTIME_PRIORITY:
> + return AIE4_CONTEXT_PRIORITY_BAND_REAL_TIME;
> + default:
> + return AIE4_CONTEXT_PRIORITY_BAND_NORMAL;
> + }
> +}
> +
> static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
> {
> DECLARE_AIE_MSG(aie4_msg_create_hw_context, AIE4_MSG_OP_CREATE_HW_CONTEXT);
> @@ -129,9 +145,8 @@ static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx)
>
> req.partition_id = ndev->partition_id;
> req.request_num_tiles = hwctx->num_tiles;
> - req.pasid = FIELD_PREP(AIE4_MSG_PASID, client->pasid) |
> - FIELD_PREP(AIE4_MSG_PASID_VLD, 1);
> - req.priority_band = hwctx->qos.priority;
> + req.pasid = aie4_msg_pasid(client);
> + req.priority_band = aie4_parse_priority_to_dev(hwctx->qos.priority);
>
> req.hsa_addr_high = upper_32_bits(amdxdna_gem_dev_addr(priv->umq_bo));
> req.hsa_addr_low = lower_32_bits(amdxdna_gem_dev_addr(priv->umq_bo));
> diff --git a/drivers/accel/amdxdna/aie4_host_queue.h b/drivers/accel/amdxdna/aie4_host_queue.h
> index 1b33eda3f727..97e535939b32 100644
> --- a/drivers/accel/amdxdna/aie4_host_queue.h
> +++ b/drivers/accel/amdxdna/aie4_host_queue.h
> @@ -10,6 +10,14 @@
>
> #define CTX_MAX_CMDS 32
>
> +/*
> + * Host queue header layout.
> + *
> + * Note: Compatibility for this layout is checked against the CERT firmware
> + * protocol version (host_queue_major/minor) via aie_check_cert_protocol(),
> + * introduced in the preceding patch ("accel/amdxdna: Add CERT firmware
> + * version support").
> + */
> struct host_queue_header {
> __u64 read_index;
> struct {
> @@ -17,8 +25,10 @@ struct host_queue_header {
> __u16 minor;
> } version;
> __u32 capacity; /* Queue capacity, must be power of two. */
> - __u64 write_index;
> + __u64 padding0[6];
> + __u64 write_index; /* different cacheline from read_index to avoid false sharing */
> + __u64 padding1[6];
> __u64 data_address; /* The xdna dev addr for payload. */
> -};
> +} __packed;
>
> #endif /* _AIE4_HOST_QUEUE_H_ */
> diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c
> index b137a2a40b34..0bb1d18df027 100644
> --- a/drivers/accel/amdxdna/aie4_message.c
> +++ b/drivers/accel/amdxdna/aie4_message.c
> @@ -5,6 +5,7 @@
>
> #include <drm/amdxdna_accel.h>
> #include <drm/drm_print.h>
> +#include <linux/bitfield.h>
> #include <linux/mutex.h>
>
> #include "aie.h"
> @@ -14,6 +15,15 @@
> #include "amdxdna_mailbox_helper.h"
> #include "amdxdna_pci_drv.h"
>
> +u32 aie4_msg_pasid(struct amdxdna_client *client)
> +{
> + if (!amdxdna_pasid_on(client))
> + return 0;
Should it return IOMMU_PASID_INVALID which is actually -1?
Lizhi
> +
> + return FIELD_PREP(AIE4_MSG_PASID, client->pasid) |
> + FIELD_PREP(AIE4_MSG_PASID_VLD, 1);
> +}
> +
> int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev)
> {
> DECLARE_AIE_MSG(aie4_msg_suspend, AIE4_MSG_OP_SUSPEND);
> diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h
> index 5b97c8057de0..b9f7c61f36e3 100644
> --- a/drivers/accel/amdxdna/aie4_msg_priv.h
> +++ b/drivers/accel/amdxdna/aie4_msg_priv.h
> @@ -12,7 +12,6 @@
> enum aie4_msg_opcode {
> AIE4_MSG_OP_IDENTIFY = 0x10002,
> AIE4_MSG_OP_SUSPEND = 0x10003,
> - AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x1000D,
> AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION = 0x1000F,
>
> AIE4_MSG_OP_CREATE_VFS = 0x20001,
> @@ -23,6 +22,8 @@ enum aie4_msg_opcode {
> AIE4_MSG_OP_CREATE_HW_CONTEXT = 0x30003,
> AIE4_MSG_OP_DESTROY_HW_CONTEXT = 0x30004,
> AIE4_MSG_OP_AIE_TILE_INFO = 0x30006,
> +
> + AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x40001,
> };
>
> enum aie4_msg_status {
> @@ -32,6 +33,14 @@ enum aie4_msg_status {
> MAX_AIE4_MSG_STATUS_CODE = 0x4,
> };
>
> +enum aie4_msg_context_priority_band {
> + AIE4_CONTEXT_PRIORITY_BAND_IDLE = 0,
> + AIE4_CONTEXT_PRIORITY_BAND_NORMAL,
> + AIE4_CONTEXT_PRIORITY_BAND_FOCUS,
> + AIE4_CONTEXT_PRIORITY_BAND_REAL_TIME,
> + AIE4_CONTEXT_PRIORITY_BAND_COUNT
> +};
> +
> struct aie4_msg_identify_req {
> __u32 rsvd;
> } __packed;
> @@ -94,7 +103,9 @@ struct aie4_msg_create_hw_context_req {
> #define AIE4_MSG_PASID GENMASK(19, 0)
> #define AIE4_MSG_PASID_VLD GENMASK(31, 31)
> __u32 pasid;
> - __u32 priority_band;
> + __u8 priority_band;
> + __u8 priority_level;
> + __u16 restore_id;
> } __packed;
>
> struct aie4_msg_create_hw_context_resp {
> @@ -106,11 +117,14 @@ struct aie4_msg_create_hw_context_resp {
>
> struct aie4_msg_destroy_hw_context_req {
> __u32 hw_context_id;
> - __u32 resvd1;
> +#define AIE4_MSG_GRACEFUL_FLAG GENMASK(0, 0)
> + __u32 graceful_flag;
> } __packed;
>
> struct aie4_msg_destroy_hw_context_resp {
> enum aie4_msg_status status;
> + __u16 restore_id;
> + __u16 resvd;
> } __packed;
>
> struct aie4_tile_info {
> diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
> index 8c62ee6a9b23..bdbb2d7cf0e7 100644
> --- a/drivers/accel/amdxdna/aie4_pci.h
> +++ b/drivers/accel/amdxdna/aie4_pci.h
> @@ -75,6 +75,7 @@ int aie4_query_npu_firmware_version(struct amdxdna_dev_hdl *ndev,
> struct amdxdna_drm_query_firmware_version *fw_version);
> int aie4_query_cert_firmware_version(struct amdxdna_dev_hdl *ndev,
> struct amdxdna_drm_query_firmware_version *cert_version);
> +u32 aie4_msg_pasid(struct amdxdna_client *client);
>
> /* aie4_ctx.c */
> int aie4_hwctx_init(struct amdxdna_hwctx *hwctx);
> diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
> index 31208c42ad5f..891c5f243ae5 100644
> --- a/drivers/accel/amdxdna/npu3_regs.c
> +++ b/drivers/accel/amdxdna/npu3_regs.c
> @@ -38,7 +38,7 @@
> #define MP1_C2PMSG_60_ALT_1 0x3B109F0
>
> static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = {
> - { .major = 5, .min_minor = 10 },
> + { .major = 6, .min_minor = 0 },
> { 0 }
> };
>
next prev parent reply other threads:[~2026-09-28 17:08 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-26 1:34 [PATCH V0 00/21] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
2026-09-26 1:34 ` [PATCH V0 01/21] accel/amdxdna: Rename NPU3 firmware files David Zhang
2026-09-26 1:34 ` [PATCH V0 02/21] accel/amdxdna: Remove mmap for doorbell David Zhang
2026-09-26 1:34 ` [PATCH V0 03/21] accel/amdxdna: Add CERT firmware version support David Zhang
2026-09-26 1:34 ` [PATCH V0 04/21] accel/amdxdna: Upgrade firmware version to 6.0 David Zhang
2026-09-28 17:08 ` Lizhi Hou [this message]
2026-09-26 1:34 ` [PATCH V0 05/21] accel/amdxdna: Add NPU3 classic device support David Zhang
2026-09-26 1:34 ` [PATCH V0 06/21] accel/amdxdna: Add AIE version query to aie4_get_info David Zhang
2026-09-26 1:34 ` [PATCH V0 07/21] accel/amdxdna: Add get and set power_mode for AIE4 David Zhang
2026-09-28 18:39 ` Lizhi Hou
2026-09-26 1:34 ` [PATCH V0 08/21] accel/amdxdna: Restore power mode override on AIE4 hardware start David Zhang
2026-09-28 18:48 ` Lizhi Hou
2026-09-26 1:34 ` [PATCH V0 09/21] accel/amdxdna: Add clock, DPM frequency, and resource info queries for AIE4 David Zhang
2026-09-26 1:34 ` [PATCH V0 10/21] accel/amdxdna: Add context switch hysteresis with debugfs control David Zhang
2026-09-26 1:34 ` [PATCH V0 11/21] accel/amdxdna: Refactor AIE4 hardware initialization sequence David Zhang
2026-09-26 1:34 ` [PATCH V0 12/21] accel/amdxdna: Decouple AIE4 doorbell and MSI-X notification transport hooks David Zhang
2026-09-28 20:16 ` Lizhi Hou
2026-09-26 1:34 ` [PATCH V0 13/21] accel/amdxdna: Implement AIE4 kernel queue lifecycle and memory layout David Zhang
2026-09-26 1:34 ` [PATCH V0 14/21] accel/amdxdna: Fix fence timeline name and context allocation David Zhang
2026-09-28 21:06 ` Lizhi Hou
2026-09-26 1:34 ` [PATCH V0 15/21] accel/amdxdna: Prepare for AIE4 command submission David Zhang
2026-09-26 1:34 ` [PATCH V0 16/21] accel/amdxdna: Implement AIE4 command packet building and submission David Zhang
2026-09-26 1:34 ` [PATCH V0 17/21] accel/amdxdna: Finalize runtime PM before acquiring dev_lock on removal David Zhang
2026-09-26 1:34 ` [PATCH V0 18/21] accel/amdxdna: Implement AIE4 suspend and resume David Zhang
2026-09-26 1:34 ` [PATCH V0 19/21] accel/amdxdna: Link SR-IOV VFs for power management sequencing David Zhang
2026-09-26 1:34 ` [PATCH V0 20/21] accel/amdxdna: Implement runtime suspend and resume support David Zhang
2026-09-26 1:34 ` [PATCH V0 21/21] accel/amdxdna: Add stub hwctx_config for AIE4 David Zhang
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