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From: Dapeng Mi <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	Dapeng Mi <dapeng1.mi@intel.com>, Zide Chen <zide.chen@intel.com>,
	Falcon Thomas <thomas.falcon@intel.com>,
	Xudong Hao <xudong.hao@intel.com>,
	Dapeng Mi <dapeng1.mi@linux.intel.com>
Subject: [PATCH 15/15] perf/x86/intel: Allow Topdown metrics with a non-leader slots event
Date: Mon, 28 Sep 2026 15:43:09 +0800	[thread overview]
Message-ID: <20260928074309.898043-16-dapeng1.mi@linux.intel.com> (raw)
In-Reply-To: <20260928074309.898043-1-dapeng1.mi@linux.intel.com>

Topdown metric events currently require the slots event to be the group
leader. That is unnecessarily strict. For metric counting, it is
sufficient that a valid slots event exists in the same group, regardless
of whether it is the leader.

Relax the validation in intel_pmu_hw_config() to accept a slots sibling
and validate metric constraints against that slots event. This enables
leader sampling for groups such as:

-e '{cycles:p,slots,topdown-retiring}:S'

Keep the existing ordering rule: the slots event must appear before all
metric events. Group validation is incremental, and intel_pmu_hw_config()
cannot determine whether the current event is the last event in the
group.

Also set the slots event with PERF_EV_CAP_RELIED_ON and metric events
with PERF_EV_CAP_RELIANT so that detaching the slots event will place
the dependent metric events into the ERROR state if slots event is not
the group leader.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
 arch/x86/events/intel/core.c | 37 +++++++++++++++++++++++++++++-------
 1 file changed, 30 insertions(+), 7 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 6cc1462c9c82..9025f29f625d 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5300,30 +5300,53 @@ static int intel_pmu_hw_config(struct perf_event *event)
 
 		if (is_available_metric_event(event)) {
 			struct perf_event *leader = event->group_leader;
+			struct perf_event *slots = NULL;
+			struct perf_event *sibling;
 
 			/* The metric events don't support sampling. */
 			if (is_sampling_event(event))
 				return -EINVAL;
 
-			/* The metric events require a slots group leader. */
-			if (!is_slots_event(leader))
+			/*
+			 * intel_pmu_hw_config() cannot tell whether the current
+			 * event is the last one in the group. Require the slots
+			 * event to appear before all metric events.
+			 */
+			if (is_slots_event(leader)) {
+				slots = leader;
+			} else if (leader->nr_siblings) {
+				for_each_sibling_event(sibling, leader) {
+					if (is_slots_event(sibling)) {
+						slots = sibling;
+						break;
+					}
+				}
+			}
+
+			/* The metric events require a slots event. */
+			if (!slots)
 				return -EINVAL;
 
 			/*
-			 * The leader/SLOTS must not be a sampling event for
+			 * The slots event must not be a sampling event for
 			 * metric use; hardware requires it starts at 0 when used
 			 * in conjunction with MSR_PERF_METRICS.
 			 */
-			if (is_sampling_event(leader))
+			if (is_sampling_event(slots))
 				return -EINVAL;
 
-			event->event_caps |= PERF_EV_CAP_SIBLING;
+			if (slots == leader) {
+				event->event_caps |= PERF_EV_CAP_SIBLING;
+			} else {
+				slots->event_caps |= PERF_EV_CAP_RELIED_ON;
+				event->event_caps |= PERF_EV_CAP_RELIANT;
+			}
 			/*
 			 * Only once we have a METRICs sibling do we
 			 * need TopDown magic.
 			 */
-			leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
-			event->hw.flags  |= PERF_X86_EVENT_TOPDOWN;
+			slots->hw.flags |= PERF_X86_EVENT_TOPDOWN;
+			event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
 		}
 	}
 
-- 
2.34.1


      parent reply	other threads:[~2026-09-28  7:51 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-28  7:42 [PATCH 00/15] perf/x86: Fix sampling bugs and relax slots-event grouping Dapeng Mi
2026-09-28  7:42 ` [PATCH 01/15] perf/x86/intel: Guard leader sibling walk on nr_siblings Dapeng Mi
2026-09-28  7:42 ` [PATCH 02/15] perf/x86/intel: Reset active_fixed_ctrl_val on CPU teardown Dapeng Mi
2026-09-28  7:42 ` [PATCH 03/15] perf/x86/intel: Reset active_pebs_data_cfg " Dapeng Mi
2026-09-28  7:42 ` [PATCH 04/15] perf/x86/intel: Reset cached acr_cfg_b[] and cfg_c_val[] " Dapeng Mi
2026-09-28  7:42 ` [PATCH 05/15] perf/x86/intel: Pass correct PEBS counter mask to no-drain update path Dapeng Mi
2026-09-28  7:43 ` [PATCH 06/15] perf/x86/intel: Limit PEBS counter iteration to valid array bounds Dapeng Mi
2026-09-28  7:43 ` [PATCH 07/15] perf/x86/intel: Reject SAMPLE_READ for no-counter-snapshot ACR events Dapeng Mi
2026-09-28  7:43 ` [PATCH 08/15] perf/x86/intel: Fix stale PEBS count without counter-group support Dapeng Mi
2026-09-28  7:43 ` [PATCH 09/15] perf/x86/intel: Refactor intel_pmu_drain_arch_pebs() Dapeng Mi
2026-09-28  7:43 ` [PATCH 10/15] perf/x86/intel: Refactor intel_pmu_drain_pebs_icl() Dapeng Mi
2026-09-28  7:43 ` [PATCH 11/15] perf/x86/intel: Fix invalid PEBS counts with counter-group support Dapeng Mi
2026-09-28  7:43 ` [PATCH 12/15] perf/x86/intel: Make ACR static_call update architectural Dapeng Mi
2026-09-28  7:43 ` [PATCH 13/15] perf/x86: Validate event type before topdown/mem-loads classification Dapeng Mi
2026-09-28  7:43 ` [PATCH 14/15] perf/core: Add event_caps dependency flags Dapeng Mi
2026-09-28  7:43 ` Dapeng Mi [this message]

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