From: Dapeng Mi <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>, Zide Chen <zide.chen@intel.com>,
Falcon Thomas <thomas.falcon@intel.com>,
Xudong Hao <xudong.hao@intel.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>
Subject: [PATCH 07/15] perf/x86/intel: Reject SAMPLE_READ for no-counter-snapshot ACR events
Date: Mon, 28 Sep 2026 15:43:01 +0800 [thread overview]
Message-ID: <20260928074309.898043-8-dapeng1.mi@linux.intel.com> (raw)
In-Reply-To: <20260928074309.898043-1-dapeng1.mi@linux.intel.com>
ACR events cannot always provide a reliable value through SAMPLE_READ.
For non-PEBS ACR events, another ACR overflow can auto-reload the counter
before software reads it, so software cannot sample the exact count before
the hardware reload.
PEBS-backed ACR events are safe only when counter snapshot support is
available, because the value is captured in the PEBS record before the
counter is reloaded.
Reject SAMPLE_READ for ACR event groups unless the event has PEBS
counter snapshot support, so perf does not report invalid counts.
Reported-by: Andi Kleen <ak@linux.intel.com>
Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload")
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 59 ++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 377ff3912420..3fc3795534bf 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4974,6 +4974,53 @@ static inline int intel_set_branch_counter_constr(struct perf_event *event,
return 0;
}
+static inline bool is_acr_sample_read_allowed(struct perf_event *event,
+ bool group_has_sample_read)
+{
+ /*
+ * ACR events cannot report an accurate count for non-PEBS events
+ * or for PEBS events without counter snapshots: another ACR event
+ * may overflow andauto-reload the counter before software can read
+ * the precise value.
+ *
+ * We keep the check simple and do not validate the acr_mask precisely
+ * to determine whether the SAMPLE_READ event is actually auto-reloaded
+ * by another ACR event. If a SAMPLE_READ event is in the group, the
+ * ACR event must be a PEBS event with counter snapshots; otherwise it
+ * is rejected.
+ */
+ if (group_has_sample_read && is_sampling_event(event) &&
+ (!event->attr.precise_ip || !is_pebs_counter_event_group(event)))
+ return false;
+
+ return true;
+}
+
+static bool intel_pmu_allow_acr_sample_read(struct perf_event *event,
+ bool group_has_sample_read)
+{
+ struct perf_event *leader = event->group_leader;
+ struct perf_event *sibling;
+
+ if (!is_acr_sample_read_allowed(leader, group_has_sample_read))
+ return false;
+
+ if (leader->nr_siblings) {
+ for_each_sibling_event(sibling, leader) {
+ if (!is_acr_sample_read_allowed(sibling,
+ group_has_sample_read))
+ return false;
+ }
+ }
+
+ /* event isn't installed as a sibling yet. */
+ if ((event != leader) &&
+ !is_acr_sample_read_allowed(event, group_has_sample_read))
+ return false;
+
+ return true;
+}
+
static int intel_pmu_hw_config(struct perf_event *event)
{
int ret = x86_pmu_hw_config(event);
@@ -5117,6 +5164,7 @@ static int intel_pmu_hw_config(struct perf_event *event)
struct perf_event *sibling, *leader = event->group_leader;
struct pmu *pmu = event->pmu;
bool has_sw_event = false;
+ bool has_sample_read = false;
int num = 0, idx = 0;
u64 cause_mask = 0;
@@ -5162,8 +5210,14 @@ static int intel_pmu_hw_config(struct perf_event *event)
if (leader->attr.config2)
intel_pmu_set_acr_cntr_constr(leader, &cause_mask, &num);
+ if ((leader->attr.sample_type & PERF_SAMPLE_READ) ||
+ (event->attr.sample_type & PERF_SAMPLE_READ))
+ has_sample_read = true;
+
if (leader->nr_siblings) {
for_each_sibling_event(sibling, leader) {
+ if (sibling->attr.sample_type & PERF_SAMPLE_READ)
+ has_sample_read = true;
if (!is_x86_event(sibling)) {
has_sw_event = true;
continue;
@@ -5175,6 +5229,7 @@ static int intel_pmu_hw_config(struct perf_event *event)
intel_pmu_set_acr_cntr_constr(sibling, &cause_mask, &num);
}
}
+
if (leader != event && event->attr.config2) {
if (has_sw_event)
return -EINVAL;
@@ -5184,6 +5239,10 @@ static int intel_pmu_hw_config(struct perf_event *event)
if (hweight64(cause_mask) > hweight64(hybrid(pmu, acr_cause_mask64)) ||
num > hweight64(hybrid(event->pmu, acr_cntr_mask64)))
return -EINVAL;
+
+ if (!intel_pmu_allow_acr_sample_read(event, has_sample_read))
+ return -EINVAL;
+
/*
* In the second round, apply the counter-constraints for
* the events which can cause other events reload.
--
2.34.1
next prev parent reply other threads:[~2026-09-28 7:50 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-28 7:42 [PATCH 00/15] perf/x86: Fix sampling bugs and relax slots-event grouping Dapeng Mi
2026-09-28 7:42 ` [PATCH 01/15] perf/x86/intel: Guard leader sibling walk on nr_siblings Dapeng Mi
2026-09-28 7:42 ` [PATCH 02/15] perf/x86/intel: Reset active_fixed_ctrl_val on CPU teardown Dapeng Mi
2026-09-28 7:42 ` [PATCH 03/15] perf/x86/intel: Reset active_pebs_data_cfg " Dapeng Mi
2026-09-28 7:42 ` [PATCH 04/15] perf/x86/intel: Reset cached acr_cfg_b[] and cfg_c_val[] " Dapeng Mi
2026-09-28 7:42 ` [PATCH 05/15] perf/x86/intel: Pass correct PEBS counter mask to no-drain update path Dapeng Mi
2026-09-28 7:43 ` [PATCH 06/15] perf/x86/intel: Limit PEBS counter iteration to valid array bounds Dapeng Mi
2026-09-28 7:43 ` Dapeng Mi [this message]
2026-09-28 7:43 ` [PATCH 08/15] perf/x86/intel: Fix stale PEBS count without counter-group support Dapeng Mi
2026-09-28 7:43 ` [PATCH 09/15] perf/x86/intel: Refactor intel_pmu_drain_arch_pebs() Dapeng Mi
2026-09-28 7:43 ` [PATCH 10/15] perf/x86/intel: Refactor intel_pmu_drain_pebs_icl() Dapeng Mi
2026-09-28 7:43 ` [PATCH 11/15] perf/x86/intel: Fix invalid PEBS counts with counter-group support Dapeng Mi
2026-09-28 7:43 ` [PATCH 12/15] perf/x86/intel: Make ACR static_call update architectural Dapeng Mi
2026-09-28 7:43 ` [PATCH 13/15] perf/x86: Validate event type before topdown/mem-loads classification Dapeng Mi
2026-09-28 7:43 ` [PATCH 14/15] perf/core: Add event_caps dependency flags Dapeng Mi
2026-09-28 7:43 ` [PATCH 15/15] perf/x86/intel: Allow Topdown metrics with a non-leader slots event Dapeng Mi
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