From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Vishal Badole <Vishal.Badole@amd.com>
Cc: bp@alien8.de, tony.luck@intel.com, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] EDAC/amd64: Set zn_regs_v2 for all Family 1Ah models
Date: Mon, 28 Sep 2026 10:21:59 -0400 [thread overview]
Message-ID: <20260928142159.GA2289128@yaz-khff2.amd.com> (raw)
In-Reply-To: <20260925172639.97063-2-Vishal.Badole@amd.com>
On Fri, Sep 25, 2026 at 10:56:38PM +0530, Vishal Badole wrote:
> The v2 register layout applies to every Family 1Ah model, but
> zn_regs_v2 is set individually in each model case of the switch. All
> currently supported models set it, so this is not a live bug; however a
> model added later without its own case, or in a case that omits the
> assignment, would read the UMC registers at the wrong offsets.
This parapragh should be simpler. Also, please avoid using long, run-on,
compound sentences.
>
> Set zn_regs_v2 once at the Family 1Ah level so it applies to all models
> uniformly, and drop the per-model assignments.
>
> No functional change intended.
>
> Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
> Signed-off-by: Vishal Badole <Vishal.Badole@amd.com>
> ---
> drivers/edac/amd64_edac.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index 475235c402e8..cab696be4f07 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -3887,23 +3887,19 @@ static int per_family_init(struct amd64_pvt *pvt)
> break;
>
> case 0x1A:
> + pvt->flags.zn_regs_v2 = 1;
> +
> switch (pvt->model) {
> case 0x00 ... 0x1f:
> pvt->max_mcs = 12;
> - pvt->flags.zn_regs_v2 = 1;
> - break;
> - case 0x40 ... 0x4f:
> - pvt->flags.zn_regs_v2 = 1;
> break;
> case 0x50 ... 0x57:
> case 0xc0 ... 0xc7:
> pvt->max_mcs = 16;
> - pvt->flags.zn_regs_v2 = 1;
> break;
> case 0x90 ... 0x9f:
> case 0xa0 ... 0xaf:
> pvt->max_mcs = 8;
> - pvt->flags.zn_regs_v2 = 1;
> break;
> }
> break;
> --
Otherwise, looks good to me.
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Thanks,
Yazen
next prev parent reply other threads:[~2026-09-28 14:22 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-25 17:26 [PATCH 0/2] EDAC/amd64: Consolidate Family 1Ah setup and fix UMC csrow decode Vishal Badole
2026-09-25 17:26 ` [PATCH 1/2] EDAC/amd64: Set zn_regs_v2 for all Family 1Ah models Vishal Badole
2026-09-28 14:21 ` Yazen Ghannam [this message]
2026-09-28 16:08 ` Badole, Vishal
2026-09-25 17:26 ` [PATCH 2/2] EDAC/amd64: Mask UMC chip select to the four implemented selects Vishal Badole
2026-09-25 18:14 ` Borislav Petkov
2026-09-28 14:38 ` Yazen Ghannam
2026-09-28 16:09 ` Badole, Vishal
2026-09-28 19:20 ` Borislav Petkov
2026-09-28 20:03 ` Yazen Ghannam
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