From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Alison Schofield <alison.schofield@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>,
linux-tegra@vger.kernel.org,
Srirangan Madhavan <smadhavan@nvidia.com>
Subject: [PATCH v14 15/16] PCI/CXL: Expose CXL Reset as a PCI reset method
Date: Thu, 1 Oct 2026 09:22:26 +0000 [thread overview]
Message-ID: <20261001092227.3004747-16-smadhavan@nvidia.com> (raw)
In-Reply-To: <20261001092227.3004747-1-smadhavan@nvidia.com>
Register cxl_reset with the PCI reset-method interface and place it before
FLR, which does not reset CXL.cache or CXL.mem protocol state.
Return -ENOTTY when device capabilities, function scope, cached HDM state,
or required cache synchronization do not permit a safe reset.
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
---
drivers/cxl/core/resource.c | 8 ++++----
drivers/pci/pci.c | 2 ++
include/linux/pci.h | 2 +-
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c
index 0acc471d0d7e..efbab341b30f 100644
--- a/drivers/cxl/core/resource.c
+++ b/drivers/cxl/core/resource.c
@@ -1264,9 +1264,9 @@ int cxl_reset_function(struct pci_dev *pdev, bool probe)
rc = pci_read_config_word(pdev, dvsec + PCI_DVSEC_CXL_CAP, &cap);
if (rc)
- return pcibios_err_to_errno(rc);
+ return probe ? -ENOTTY : pcibios_err_to_errno(rc);
if (PCI_POSSIBLE_ERROR(cap))
- return -ENODEV;
+ return probe ? -ENOTTY : -ENODEV;
if (!(cap & PCI_DVSEC_CXL_CACHE_CAPABLE) ||
!(cap & PCI_DVSEC_CXL_MEM_CAPABLE) ||
!(cap & PCI_DVSEC_CXL_RST_CAPABLE) ||
@@ -1275,9 +1275,9 @@ int cxl_reset_function(struct pci_dev *pdev, bool probe)
rc = pci_read_config_word(pdev, dvsec + PCI_DVSEC_CXL_CTRL, &ctrl);
if (rc)
- return pcibios_err_to_errno(rc);
+ return probe ? -ENOTTY : pcibios_err_to_errno(rc);
if (PCI_POSSIBLE_ERROR(ctrl))
- return -ENODEV;
+ return probe ? -ENOTTY : -ENODEV;
if (!(ctrl & PCI_DVSEC_CXL_CACHE_ENABLE) ||
!(ctrl & PCI_DVSEC_CXL_MEM_ENABLE))
return -ENOTTY;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index fe611340f5ab..dc57a202c91f 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -35,6 +35,7 @@
#include <linux/aer.h>
#include <linux/bitfield.h>
#include <linux/suspend.h>
+#include <cxl/cxl.h>
#include "pci.h"
DEFINE_MUTEX(pci_slot_mutex);
@@ -5148,6 +5149,7 @@ const struct pci_reset_fn_method pci_reset_fn_methods[] = {
{ },
{ pci_dev_specific_reset, .name = "device_specific" },
{ pci_dev_acpi_reset, .name = "acpi" },
+ { cxl_reset_function, .name = "cxl_reset" },
{ pcie_reset_flr, .name = "flr" },
{ pci_af_flr, .name = "af_flr" },
{ pci_pm_reset, .name = "pm" },
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 7bb37fcb556d..743b57ff885a 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -52,7 +52,7 @@
PCI_STATUS_PARITY)
/* Number of reset methods used in pci_reset_fn_methods array in pci.c */
-#define PCI_NUM_RESET_METHODS 8
+#define PCI_NUM_RESET_METHODS 9
#define PCI_RESET_PROBE true
#define PCI_RESET_DO_RESET false
--
2.43.0
next prev parent reply other threads:[~2026-10-01 9:23 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-01 9:22 [PATCH v14 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 05/16] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 06/16] cxl: Move HDM decoder helpers to built-in resource code Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 08/16] cxl: Reject overflowing HDM decoder ranges Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 09/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 10/16] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 11/16] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 12/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 13/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 14/16] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-01 9:22 ` Srirangan Madhavan [this message]
2026-10-01 9:22 ` [PATCH v14 16/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
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