From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Alison Schofield <alison.schofield@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>,
linux-tegra@vger.kernel.org,
Srirangan Madhavan <smadhavan@nvidia.com>,
Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Subject: [PATCH v14 01/16] cxl: Drop stale decoder interleave limit comment
Date: Thu, 1 Oct 2026 09:22:12 +0000 [thread overview]
Message-ID: <20261001092227.3004747-2-smadhavan@nvidia.com> (raw)
In-Reply-To: <20261001092227.3004747-1-smadhavan@nvidia.com>
CXL 2.0 added 16-way memory interleaving, making the comment that the
specification supports only 8-way interleaving stale. Remove the comment
without changing CXL_DECODER_MAX_INTERLEAVE.
Suggested-by: Jonathan Cameron <jic23@kernel.org>
Link: https://lore.kernel.org/linux-cxl/20260912003057.3db9335c@jic23-hlaptop/
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/cxl.h | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 3ef0810ab86b..9e0500d56866 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -269,10 +269,6 @@ enum cxl_decoder_type {
CXL_DECODER_HOSTONLYMEM = 3,
};
-/*
- * Current specification goes up to 8, double that seems a reasonable
- * software max for the foreseeable future
- */
#define CXL_DECODER_MAX_INTERLEAVE 16
#define CXL_QOS_CLASS_INVALID -1
base-commit: fef22d37d47043b63e4007f2f5fe762fa21fae0c
--
2.43.0
next prev parent reply other threads:[~2026-10-01 9:22 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-01 9:22 [PATCH v14 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-01 9:22 ` Srirangan Madhavan [this message]
2026-10-01 9:22 ` [PATCH v14 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 05/16] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 06/16] cxl: Move HDM decoder helpers to built-in resource code Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 08/16] cxl: Reject overflowing HDM decoder ranges Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 09/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 10/16] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 11/16] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 12/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 13/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 14/16] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 15/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 16/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
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