From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Changhuang Liang <changhuang.liang@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>
Subject: [PATCH v6 4/5] reset: starfive: Introduce active_low
Date: Sat, 10 Oct 2026 03:58:58 -0700 [thread overview]
Message-ID: <20261010105859.19505-5-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20261010105859.19505-1-changhuang.liang@starfivetech.com>
The JHB100 SoC supports inverted operations for reset
assertion/deassertion, introducing an active_low field to distinguish
between different operation logics.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/reset/starfive/reset-starfive-jh71x0.c | 3 ++-
drivers/reset/starfive/reset-starfive-jh71x0.h | 6 ++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c
index fd1c755a0017..f48959b66f7c 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.c
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
@@ -52,6 +52,7 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
+ bool active_low = data->info && data->info->active_low;
unsigned long offset, flags;
void __iomem *reg_assert;
void __iomem *reg_status;
@@ -76,7 +77,7 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
spin_lock_irqsave(&data->lock, flags);
value = readl(reg_assert);
- if (assert)
+ if (assert != active_low)
value |= mask;
else
value &= ~mask;
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
index 36f198139602..7a967eeb3181 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
@@ -15,6 +15,12 @@ struct jh71x0_reset_info {
unsigned int nr_resets;
unsigned int assert_offset;
unsigned int status_offset;
+
+ /*
+ * If true, the reset is asserted by clearing the bit and deasserted
+ * by setting it. If false, it is the other way around.
+ */
+ bool active_low;
bool discontiguous;
const struct jh71x0_reset_map *map;
};
--
2.25.1
next prev parent reply other threads:[~2026-10-10 11:14 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-10 10:58 [PATCH v6 0/5] Add StarFive JHB100 syscon modules Changhuang Liang
2026-10-10 10:58 ` [PATCH v6 1/5] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
2026-10-10 10:58 ` [PATCH v6 2/5] clk: starfive: Add Peripheral-0 " Changhuang Liang
2026-10-10 10:58 ` [PATCH v6 3/5] clk: starfive: Add Peripheral-1 " Changhuang Liang
2026-10-10 10:58 ` Changhuang Liang [this message]
2026-10-10 10:58 ` [PATCH v6 5/5] reset: starfive: Add syscon reset driver support Changhuang Liang
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