From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Changhuang Liang <changhuang.liang@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>
Subject: [PATCH v6 5/5] reset: starfive: Add syscon reset driver support
Date: Sat, 10 Oct 2026 03:58:59 -0700 [thread overview]
Message-ID: <20261010105859.19505-6-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20261010105859.19505-1-changhuang.liang@starfivetech.com>
Add syscon reset driver for JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/reset/starfive/Kconfig | 9 +++
drivers/reset/starfive/Makefile | 1 +
.../starfive/reset-starfive-jhb100-syscon.c | 61 +++++++++++++++++++
3 files changed, 71 insertions(+)
create mode 100644 drivers/reset/starfive/reset-starfive-jhb100-syscon.c
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index 84baefbaee14..be948b855c79 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -28,3 +28,12 @@ config RESET_STARFIVE_JHB100
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JHB100 SoC.
+
+config RESET_STARFIVE_JHB100_SYSCON
+ tristate "StarFive JHB100 SYSCON Reset Driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select RESET_STARFIVE_JH71X0
+ default m if ARCH_STARFIVE
+ help
+ This enables the SYSCON reset controller driver for the StarFive
+ JHB100 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index d781103355d3..f568938d0219 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
obj-$(CONFIG_RESET_STARFIVE_JHB100) += reset-starfive-jhb100.o
+obj-$(CONFIG_RESET_STARFIVE_JHB100_SYSCON) += reset-starfive-jhb100-syscon.o
diff --git a/drivers/reset/starfive/reset-starfive-jhb100-syscon.c b/drivers/reset/starfive/reset-starfive-jhb100-syscon.c
new file mode 100644
index 000000000000..16b2333d27fe
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jhb100-syscon.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * SYSCON Reset driver for the StarFive JHB100 SoC
+ *
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ */
+
+#include <dt-bindings/reset/starfive,jhb100-crg.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+
+#include "reset-starfive-jh71x0.h"
+
+static const struct jh71x0_reset_info jhb100_pcierp_info = {
+ .nr_resets = (JHB100_PCIERP_SYSCONRST_PE2RST_OUT + 1),
+ .assert_offset = 0x14c,
+ .status_offset = 0x14c,
+ .active_low = true,
+};
+
+static int jhb100_syscon_reset_probe(struct platform_device *pdev)
+{
+ const struct jh71x0_reset_info *info;
+ void __iomem *base;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ info = device_get_match_data(&pdev->dev);
+ if (!info)
+ return -ENODEV;
+
+ return reset_starfive_jh71x0_register_with_info(&pdev->dev, pdev->dev.of_node,
+ base + info->assert_offset,
+ base + info->status_offset,
+ NULL, info, THIS_MODULE);
+}
+
+static const struct of_device_id jhb100_syscon_reset_dt_ids[] = {
+ {
+ .compatible = "starfive,jhb100-pcierp-syscon",
+ .data = &jhb100_pcierp_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_syscon_reset_dt_ids);
+
+static struct platform_driver jhb100_syscon_reset_driver = {
+ .probe = jhb100_syscon_reset_probe,
+ .driver = {
+ .name = "jhb100-syscon-reset",
+ .of_match_table = jhb100_syscon_reset_dt_ids,
+ },
+};
+module_platform_driver(jhb100_syscon_reset_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 SYSCON reset driver");
+MODULE_LICENSE("GPL");
--
2.25.1
prev parent reply other threads:[~2026-10-10 10:59 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-10 10:58 [PATCH v6 0/5] Add StarFive JHB100 syscon modules Changhuang Liang
2026-10-10 10:58 ` [PATCH v6 1/5] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
2026-10-10 10:58 ` [PATCH v6 2/5] clk: starfive: Add Peripheral-0 " Changhuang Liang
2026-10-10 10:58 ` [PATCH v6 3/5] clk: starfive: Add Peripheral-1 " Changhuang Liang
2026-10-10 10:58 ` [PATCH v6 4/5] reset: starfive: Introduce active_low Changhuang Liang
2026-10-10 10:58 ` Changhuang Liang [this message]
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