[PATCH v6 3/5] clk: starfive: Add Peripheral-1 domain PLL clock driver

[Changhuang Liang <changhuang.liang@starfivetech.com>]

Add Peripheral-1 domain PLL clock driver support for StarFive JHB100
SoC. The peripheral PLL driver now also binds to the per1 system
controller node and registers PLL7 using the JHB100 PLL library.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 drivers/clk/starfive/Kconfig                  |  8 ++++----
 .../starfive/clk-starfive-jhb100-per-pll.c    | 19 +++++++++++++++++++
 2 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 00c46f5ec976..1bf64f1b6c58 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -120,10 +120,10 @@ config CLK_STARFIVE_JHB100_PER_PLL
 	select MFD_SYSCON
 	default ARCH_STARFIVE
 	help
-	  Say yes here to support the PLL6 clock generator found in the
-	  peripheral-0 system controller of the StarFive JHB100 SoC. It
-	  provides the parent clock of the peripheral-0 clock
-	  controller.
+	  Say yes here to support the PLL6 and PLL7 clock generators found
+	  in the peripheral-0 and peripheral-1 system controllers of the
+	  StarFive JHB100 SoC. They provide the parent clocks of the
+	  peripheral-0 and peripheral-1 clock controllers.
 
 config CLK_STARFIVE_JHB100_PLL
 	bool
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-per-pll.c
index d38116f16935..ef01f7d1d5f6 100644
--- a/drivers/clk/starfive/clk-starfive-jhb100-per-pll.c
+++ b/drivers/clk/starfive/clk-starfive-jhb100-per-pll.c
@@ -19,6 +19,7 @@
 #include "clk-starfive-jhb100-pll.h"
 
 #define JHB100_PLL6_OFFSET		0x00
+#define JHB100_PLL7_OFFSET		0x40
 
 struct jhb100_per_pll_data {
 	const struct jhb100_pll_info *info;
@@ -39,6 +40,20 @@ static const struct jhb100_per_pll_data jhb100_per0_pll_data = {
 	.num = ARRAY_SIZE(jhb100_per0_pll_info),
 };
 
+static const struct jhb100_pll_mult jhb100_pll7_mults[] = {
+	{ .fbdiv = 156, .frac = 0, .refdiv = 1 },
+};
+
+static const struct jhb100_pll_info jhb100_per1_pll_info[] = {
+	JHB100_PLL(JHB100_PER1PLL_PLL7_OUT, "pll7", JHB100_PLL7_OFFSET,
+		   jhb100_pll7_mults, ARRAY_SIZE(jhb100_pll7_mults)),
+};
+
+static const struct jhb100_per_pll_data jhb100_per1_pll_data = {
+	.info = jhb100_per1_pll_info,
+	.num = ARRAY_SIZE(jhb100_per1_pll_info),
+};
+
 static int jhb100_per_pll_probe(struct platform_device *pdev)
 {
 	const struct jhb100_per_pll_data *data;
@@ -62,6 +77,10 @@ static const struct of_device_id jhb100_per_pll_match[] = {
 		.compatible = "starfive,jhb100-per0-syscon",
 		.data = &jhb100_per0_pll_data,
 	},
+	{
+		.compatible = "starfive,jhb100-per1-syscon",
+		.data = &jhb100_per1_pll_data,
+	},
 	{ /* sentinel */ }
 };
 
-- 
2.25.1