* [PATCH v16 1/8] cxl/mbox: Flag support for Dynamic Capacity Devices (DCD)
2026-10-10 22:54 [PATCH v16 0/8] DCD Prep Series Anisa Su
@ 2026-10-10 22:54 ` Anisa Su
2026-10-10 22:54 ` [PATCH v16 2/8] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
` (8 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Anisa Su @ 2026-10-10 22:54 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
From: Ira Weiny <iweiny@kernel.org>
Per the CXL 4.0 specification software must check the Command Effects
Log (CEL) for dynamic capacity command support.
Detect support for the DCD commands while reading the CEL, including:
Get DC Config
Get DC Extent List
Add DC Response
Release DC
Leave mds->dcd_supported false. Dynamic capacity is only usable once
the driver can handle Add and Release Capacity events. Detect and log
the capability here and let the commit which adds DCD event handling set
the flag.
Based on an original patch by Navneet Singh.
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Tested-by: Wonjae Lee <wj28.lee@samsung.com>
Tested-by: Junhee Park <jh9934.park@samsung.com>
Tested-by: Heesoo Kim <habil.kim@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Gregory Price (Meta) <gourry@gourry.net>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Reviewed-by: Richard Cheng <icheng@nvidia.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
---
drivers/cxl/core/mbox.c | 39 +++++++++++++++++++++++++++++++++++++++
drivers/cxl/cxlmem.h | 20 ++++++++++++++++++++
2 files changed, 59 insertions(+)
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index 55828a836c01..199bb986d674 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -171,6 +171,33 @@ static void cxl_set_security_cmd_enabled(struct cxl_security_state *security,
}
}
+static bool cxl_is_dcd_command(u16 opcode)
+{
+#define CXL_MBOX_OP_DCD_CMDS 0x48
+
+ return (opcode >> 8) == CXL_MBOX_OP_DCD_CMDS;
+}
+
+static void cxl_set_dcd_cmd_enabled(u16 opcode, unsigned long *cmd_mask)
+{
+ switch (opcode) {
+ case CXL_MBOX_OP_GET_DC_CONFIG:
+ set_bit(CXL_DCD_ENABLED_GET_CONFIG, cmd_mask);
+ break;
+ case CXL_MBOX_OP_GET_DC_EXTENT_LIST:
+ set_bit(CXL_DCD_ENABLED_GET_EXTENT_LIST, cmd_mask);
+ break;
+ case CXL_MBOX_OP_ADD_DC_RESPONSE:
+ set_bit(CXL_DCD_ENABLED_ADD_RESPONSE, cmd_mask);
+ break;
+ case CXL_MBOX_OP_RELEASE_DC:
+ set_bit(CXL_DCD_ENABLED_RELEASE, cmd_mask);
+ break;
+ default:
+ break;
+ }
+}
+
static bool cxl_is_poison_command(u16 opcode)
{
#define CXL_MBOX_OP_POISON_CMDS 0x43
@@ -759,6 +786,7 @@ static void cxl_walk_cel(struct cxl_memdev_state *mds, size_t size, u8 *cel)
struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
struct cxl_cel_entry *cel_entry;
const int cel_entries = size / sizeof(*cel_entry);
+ DECLARE_BITMAP(dcd_cmds, CXL_DCD_ENABLED_MAX) = {};
struct device *dev = mds->cxlds.dev;
int i, ro_cmds = 0, wr_cmds = 0;
@@ -787,11 +815,22 @@ static void cxl_walk_cel(struct cxl_memdev_state *mds, size_t size, u8 *cel)
enabled++;
}
+ if (cxl_is_dcd_command(opcode)) {
+ cxl_set_dcd_cmd_enabled(opcode, dcd_cmds);
+ enabled++;
+ }
+
dev_dbg(dev, "Opcode 0x%04x %s\n", opcode,
enabled ? "enabled" : "unsupported by driver");
}
set_features_cap(cxl_mbox, ro_cmds, wr_cmds);
+ /*
+ * Disabled until event handling implemented.
+ */
+ if (bitmap_full(dcd_cmds, CXL_DCD_ENABLED_MAX))
+ dev_dbg(dev, "Device supports DCD; capability disabled\n");
+ mds->dcd_supported = false;
}
static struct cxl_mbox_get_supported_logs *cxl_get_gsl(struct cxl_memdev_state *mds)
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index c401e3a1af06..0c8e23276dc6 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -252,6 +252,20 @@ struct cxl_event_state {
struct mutex log_lock;
};
+/*
+ * CXL r4.0 Section 8.2.10.9 - Memory Device Command Sets. See Table 8-308.
+ *
+ * The 48h Command Set (Opcodes 4800h - 4803h) defines the device-enabled DCD
+ * commands.
+ */
+enum dcd_cmd_enabled_bits {
+ CXL_DCD_ENABLED_GET_CONFIG,
+ CXL_DCD_ENABLED_GET_EXTENT_LIST,
+ CXL_DCD_ENABLED_ADD_RESPONSE,
+ CXL_DCD_ENABLED_RELEASE,
+ CXL_DCD_ENABLED_MAX
+};
+
/* Device enabled poison commands */
enum poison_cmd_enabled_bits {
CXL_POISON_ENABLED_LIST,
@@ -427,6 +441,7 @@ static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox)
* @partition_align_bytes: alignment size for partition-able capacity
* @active_volatile_bytes: sum of hard + soft volatile
* @active_persistent_bytes: sum of hard + soft persistent
+ * @dcd_supported: all DCD commands are supported
* @event: event log driver state
* @poison: poison driver state info
* @security: security driver state info
@@ -445,6 +460,7 @@ struct cxl_memdev_state {
u64 partition_align_bytes;
u64 active_volatile_bytes;
u64 active_persistent_bytes;
+ bool dcd_supported;
struct cxl_event_state event;
struct cxl_poison_state poison;
@@ -505,6 +521,10 @@ enum cxl_opcode {
CXL_MBOX_OP_UNLOCK = 0x4503,
CXL_MBOX_OP_FREEZE_SECURITY = 0x4504,
CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505,
+ CXL_MBOX_OP_GET_DC_CONFIG = 0x4800,
+ CXL_MBOX_OP_GET_DC_EXTENT_LIST = 0x4801,
+ CXL_MBOX_OP_ADD_DC_RESPONSE = 0x4802,
+ CXL_MBOX_OP_RELEASE_DC = 0x4803,
CXL_MBOX_OP_MAX = 0x10000
};
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v16 2/8] cxl/mem: Read dynamic capacity configuration from the device
2026-10-10 22:54 [PATCH v16 0/8] DCD Prep Series Anisa Su
2026-10-10 22:54 ` [PATCH v16 1/8] cxl/mbox: Flag support for Dynamic Capacity Devices (DCD) Anisa Su
@ 2026-10-10 22:54 ` Anisa Su
2026-10-12 11:47 ` Jonathan Cameron
2026-10-10 22:54 ` [PATCH v16 3/8] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
` (7 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Anisa Su @ 2026-10-10 22:54 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
From: Ira Weiny <iweiny@kernel.org>
Devices which support Dynamic Capacity (DC) are configured via mailbox
commands. CXL r4.0 section 9.13.3 describes the use of the Get DC
Configuration command in order to obtain DCD partition characteristics.
Implement the DC mailbox commands as specified in CXL 4.0 section
8.2.10.9.9 (opcodes 48XXh) to read and store the DCD configuration
information. Disable DCD if an invalid configuration is found.
Initial enablement for Linux only supports one dynamic capacity
partition. Read all the partitions the device reports but validate
only the first, and configure it as 'dynamic ram'.
The specification requires that volatile capacity starts at DPA 0 and
pmem starts at the DPA immediately following it, but DC partitions only
need to be 256MB aligned according to CXL r4.0 section 8.2.10.9.9.1
Table 8-347. So a device could leave a gap between ram/pmem (static)
capacity and its first DC partition, or between one DC partition and
the next.
However, Linux chooses not to support gaps between static and dynamic
capacity, and requires the first DC partition to begin at the DPA
immediately following static capacity.
Based on an original patch by Navneet Singh.
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Co-developed-by: Anisa Su <anisa.su@samsung.com>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Tested-by: Wonjae Lee <wj28.lee@samsung.com>
Tested-by: Junhee Park <jh9934.park@samsung.com>
Tested-by: Heesoo Kim <habil.kim@samsung.com>
---
Changes:
1. cxl_configure_dcd(): take the end of static capacity from the last
static partition rather than from Identify Total Capacity, which is
only required to be >= ram + pmem. A device with unpartitioned
static capacity and its DC partition right after pmem was rejected
as overlapping, and one with the DC partition at Total Capacity
passed here but failed cxl_dpa_setup() and lost the whole memdev.
The DPA space is extended to the DC partition end.
[Richard]
---
drivers/cxl/core/hdm.c | 13 ++-
drivers/cxl/core/mbox.c | 237 ++++++++++++++++++++++++++++++++++++++
drivers/cxl/core/memdev.c | 53 +++++++++
drivers/cxl/cxlmem.h | 55 +++++++++
drivers/cxl/pci.c | 6 +
include/cxl/cxl.h | 3 +-
6 files changed, 365 insertions(+), 2 deletions(-)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 0c80b76a5f9b..5fa2177cefcc 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -446,6 +446,8 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode)
return "ram";
case CXL_PARTMODE_PMEM:
return "pmem";
+ case CXL_PARTMODE_DYNAMIC_RAM:
+ return "dynamic_ram";
default:
return "";
};
@@ -455,6 +457,7 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode)
int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
{
struct device *dev = cxlds->dev;
+ int dc_nth = 0;
guard(rwsem_write)(&cxl_rwsem.dpa);
@@ -471,8 +474,16 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
for (int i = 0; i < info->nr_partitions; i++) {
const struct cxl_dpa_part_info *part = &info->part[i];
+ const char *name = cxl_mode_name(part->mode);
int rc;
+ if (part->mode == CXL_PARTMODE_DYNAMIC_RAM) {
+ name = devm_kasprintf(dev, GFP_KERNEL, "%s_%d", name,
+ ++dc_nth);
+ if (!name)
+ return -ENOMEM;
+ }
+
cxlds->part[i].perf.qos_class = CXL_QOS_CLASS_INVALID;
cxlds->part[i].mode = part->mode;
@@ -485,7 +496,7 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
}
rc = add_dpa_res(dev, &cxlds->dpa_res, &cxlds->part[i].res,
part->range.start, range_len(&part->range),
- cxl_mode_name(part->mode));
+ name);
if (rc)
return rc;
cxlds->nr_partitions++;
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index 199bb986d674..72af23ba288e 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -1349,6 +1349,243 @@ int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd)
return -EBUSY;
}
+/*
+ * A partition unavailable for Dynamic Capacity reports zeros for decode_length,
+ * length, and block_size.
+ */
+static bool cxl_dc_partition_unavailable(struct cxl_dc_partition *dev_part)
+{
+ return !le64_to_cpu(dev_part->decode_length) &&
+ !le64_to_cpu(dev_part->length) &&
+ !le64_to_cpu(dev_part->block_size);
+}
+
+static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part,
+ struct cxl_dc_partition *dev_part)
+{
+ u64 decode_len = le64_to_cpu(dev_part->decode_length);
+ u64 blk_size = le64_to_cpu(dev_part->block_size);
+ u64 len = le64_to_cpu(dev_part->length);
+ u64 size;
+
+ /*
+ * Not an error; leave the entry empty. A partially zeroed partition
+ * is rejected by the checks below. CXL r4.0 Table 8-347.
+ */
+ if (cxl_dc_partition_unavailable(dev_part)) {
+ *part = (struct cxl_dc_partition_info) { };
+ dev_dbg(dev, "Partition 0 unavailable for DC\n");
+ return 0;
+ }
+
+ /*
+ * Decode length is a count of 256M units, so a device reporting 2^36
+ * or more wraps.
+ */
+ if (check_mul_overflow(decode_len, (u64)CXL_CAPACITY_MULTIPLIER, &size)) {
+ dev_err(dev, "DC partition 0 decode length %#llx overflows\n",
+ decode_len);
+ return -EINVAL;
+ }
+
+ *part = (struct cxl_dc_partition_info) {
+ .start = le64_to_cpu(dev_part->base),
+ .size = size,
+ };
+
+ /*
+ * Block size is a power of 2 and a multiple of 40h. is_power_of_2()
+ * takes an unsigned long, which truncates blk_size on 32 bit.
+ */
+ if (blk_size == 0 || (blk_size & (blk_size - 1)) ||
+ blk_size % CXL_DCD_BLOCK_LINE_SIZE) {
+ dev_err(dev, "DC partition 0 invalid block size %#llx\n", blk_size);
+ return -EINVAL;
+ }
+
+ if (part->size == 0) {
+ dev_err(dev, "DC partition 0 zero decode length\n");
+ return -EINVAL;
+ }
+
+ if (len == 0) {
+ dev_err(dev, "DC partition 0 zero length\n");
+ return -EINVAL;
+ }
+
+ if (len > part->size) {
+ dev_err(dev, "DC partition 0 length %#llx exceeds decode length %#llx\n",
+ len, part->size);
+ return -EINVAL;
+ }
+
+ if (!IS_ALIGNED(len, blk_size)) {
+ dev_err(dev, "DC partition 0 length %#llx not a multiple of block size %#llx\n",
+ len, blk_size);
+ return -EINVAL;
+ }
+
+ if (!IS_ALIGNED(part->start, SZ_256M)) {
+ dev_err(dev, "DC partition 0 base %#llx not aligned to 256M\n",
+ part->start);
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "DC partition 0 start %#llx size %#llx blk_size: %#llx\n",
+ part->start, part->size, blk_size);
+
+ return 0;
+}
+
+/* Returns the number of partitions in dc_resp or -ERRNO */
+static int cxl_get_dc_config(struct cxl_mailbox *mbox, u8 start_partition,
+ u8 partition_count,
+ struct cxl_mbox_get_dc_config_out *dc_resp,
+ size_t dc_resp_size)
+{
+ struct cxl_mbox_get_dc_config_in get_dc = (struct cxl_mbox_get_dc_config_in) {
+ .partition_count = partition_count,
+ .start_partition_index = start_partition,
+ };
+ struct cxl_mbox_cmd mbox_cmd = (struct cxl_mbox_cmd) {
+ .opcode = CXL_MBOX_OP_GET_DC_CONFIG,
+ .payload_in = &get_dc,
+ .size_in = sizeof(get_dc),
+ .size_out = dc_resp_size,
+ .payload_out = dc_resp,
+ /* The device must return at least the fixed header */
+ .min_out = sizeof(*dc_resp),
+ };
+ size_t expected_sz;
+ int rc;
+
+ rc = cxl_internal_send_cmd(mbox, &mbox_cmd);
+ if (rc < 0)
+ return rc;
+
+ if (dc_resp->partitions_returned > partition_count) {
+ dev_err(mbox->host, "Device returned %u partitions, requested %u\n",
+ dc_resp->partitions_returned, partition_count);
+ return -EIO;
+ }
+
+ /* The trailing extent/tag counts (CXL r4.0 Table 8-346) are not read */
+ expected_sz = struct_size(dc_resp, partition,
+ dc_resp->partitions_returned);
+
+ if (mbox_cmd.size_out < expected_sz) {
+ dev_err(mbox->host,
+ "Payload size %zu less than expected %zu for %u partitions\n",
+ mbox_cmd.size_out,
+ expected_sz,
+ dc_resp->partitions_returned);
+ return -EIO;
+ }
+
+ dev_dbg(mbox->host, "Read %d/%d DC partitions\n",
+ dc_resp->partitions_returned, dc_resp->avail_partition_count);
+ return dc_resp->partitions_returned;
+}
+
+/**
+ * cxl_dev_dc_identify() - Reads the dynamic capacity information from the
+ * device.
+ * @mbox: Mailbox to query
+ * @dc_info: The dynamic partition information to return
+ *
+ * Read every partition the device reports, but validate only the first:
+ * Linux maps partition 0 and nothing else, so a defect in capacity the
+ * driver never touches is not a reason to refuse the device dynamic
+ * capacity. The remaining partitions are read but not recorded.
+ *
+ * Return: 0 if identify was executed successfully, -ERRNO on error.
+ * On error, @dc_info is left unchanged.
+ */
+int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
+ struct cxl_dc_partition_info *dc_info)
+{
+ struct cxl_dc_partition_info partitions[CXL_MAX_DC_PARTITIONS] = { };
+ struct cxl_mbox_get_dc_config_out *dc_resp __free(kfree) = NULL;
+ struct device *dev = mbox->host;
+ u8 avail_partitions = 0;
+ u8 start_partition;
+ u8 num_partitions;
+ u8 partition_count;
+ size_t dc_resp_size;
+
+ /*
+ * Bound requested number of partitions by mailbox payload size. The
+ * 256 byte spec minimum, verified in cxl_pci_setup_mailbox(), keeps
+ * the subtraction below from underflowing.
+ */
+ partition_count = min(CXL_MAX_DC_PARTITIONS,
+ (mbox->payload_size - sizeof(*dc_resp) -
+ sizeof(struct cxl_mbox_get_dc_config_tail)) /
+ sizeof(struct cxl_dc_partition));
+ dc_resp_size = struct_size(dc_resp, partition, partition_count) +
+ sizeof(struct cxl_mbox_get_dc_config_tail);
+
+ dc_resp = kmalloc(dc_resp_size, GFP_KERNEL);
+ if (!dc_resp)
+ return -ENOMEM;
+
+ start_partition = 0;
+ num_partitions = 0;
+ do {
+ int returned, rc;
+
+ returned = cxl_get_dc_config(mbox, start_partition,
+ partition_count, dc_resp,
+ dc_resp_size);
+ if (returned < 0) {
+ dev_err(dev, "Failed to get DC config: %d\n", returned);
+ return returned;
+ }
+
+ if (returned == 0) {
+ dev_err(dev,
+ "Device reported %u partitions available but returned none at index %u\n",
+ dc_resp->avail_partition_count, start_partition);
+ return -EIO;
+ }
+
+ /* A DCD reports at least one partition (CXL r4.0 Table 8-346) */
+ if (dc_resp->avail_partition_count == 0) {
+ dev_err(dev, "Device reported no DC partitions\n");
+ return -EIO;
+ }
+
+ avail_partitions = min(dc_resp->avail_partition_count,
+ CXL_MAX_DC_PARTITIONS);
+
+ /*
+ * Only partition 0 is mapped, so it is the only one checked.
+ * The rest are read to complete the enumeration and dropped.
+ */
+ if (start_partition == 0) {
+ rc = cxl_dc_check(dev, &partitions[0],
+ &dc_resp->partition[0]);
+ if (rc)
+ return rc;
+ }
+
+ num_partitions += returned;
+ start_partition = num_partitions;
+
+ } while (num_partitions < avail_partitions);
+
+ /* Linux only supports the 1st partition; nothing to do if it is unavailable */
+ if (partitions[0].size == 0)
+ return -ENODEV;
+
+ *dc_info = partitions[0];
+ dev_dbg(dev, "Returning partition 0 %#llx size %#llx\n",
+ dc_info->start, dc_info->size);
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_dev_dc_identify, "CXL");
+
int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count)
{
struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
index b3419df586b9..469767f1de70 100644
--- a/drivers/cxl/core/memdev.c
+++ b/drivers/cxl/core/memdev.c
@@ -643,6 +643,59 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
}
EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_fetch, "CXL");
+int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
+{
+ struct cxl_dc_partition_info dc_info = { };
+ struct device *dev = mds->cxlds.dev;
+ u64 static_end = 0;
+ u64 dc_end;
+ int rc;
+
+ if (!mds->cxlds.media_ready)
+ return 0;
+
+ rc = cxl_dev_dc_identify(&mds->cxlds.cxl_mbox, &dc_info);
+ if (rc) {
+ dev_warn(dev,
+ "Failed to read Dynamic Capacity config: %d\n", rc);
+ return rc;
+ }
+
+ if (info->nr_partitions)
+ static_end = info->part[info->nr_partitions - 1].range.end + 1;
+
+ if (dc_info.start < static_end) {
+ dev_err(dev,
+ "DC partition 0 base %#llx overlaps static capacity ending at %#llx\n",
+ dc_info.start, static_end);
+ return -EINVAL;
+ }
+
+ /* A gap between static capacity and the DC partition is not supported */
+ if (dc_info.start > static_end) {
+ dev_warn(dev,
+ "DC partition 0 base %#llx leaves a gap from static capacity ending at %#llx\n",
+ dc_info.start, static_end);
+ return -EOPNOTSUPP;
+ }
+
+ if (check_add_overflow(dc_info.start, dc_info.size, &dc_end)) {
+ dev_err(dev,
+ "DC partition 0 size %#llx overflows DPA space at base %#llx\n",
+ dc_info.size, dc_info.start);
+ return -EINVAL;
+ }
+
+ /* The DPA space must reach the end of the DC partition */
+ if (dc_end > info->size)
+ info->size = dc_end;
+ dev_dbg(dev, "Adding dynamic ram partition; %#llx size %#llx\n",
+ dc_info.start, dc_info.size);
+ add_part(info, dc_info.start, dc_info.size, CXL_PARTMODE_DYNAMIC_RAM);
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_configure_dcd, "CXL");
/**
* cxl_set_capacity: initialize dpa by a driver without a mailbox.
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 0c8e23276dc6..4fac65dbb808 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -407,6 +407,8 @@ struct cxl_security_state {
struct kernfs_node *sanitize_node;
};
+#define CXL_MAX_DC_PARTITIONS 8
+
static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
{
/*
@@ -689,6 +691,39 @@ struct cxl_mbox_set_shutdown_state_in {
u8 state;
} __packed;
+/* See CXL r4.0 Table 8-345 get dynamic capacity config Input Payload */
+struct cxl_mbox_get_dc_config_in {
+ u8 partition_count;
+ u8 start_partition_index;
+} __packed;
+
+/* See CXL r4.0 Table 8-346 get dynamic capacity config Output Payload */
+struct cxl_mbox_get_dc_config_out {
+ u8 avail_partition_count;
+ u8 partitions_returned;
+ u8 rsvd[6];
+ /* See CXL r4.0 Table 8-347 */
+ struct cxl_dc_partition {
+ __le64 base;
+ __le64 decode_length;
+ __le64 length;
+ __le64 block_size;
+ __le32 dsmad_handle;
+ u8 flags;
+ u8 rsvd[3];
+ } __packed partition[] __counted_by(partitions_returned);
+ /* Trailing extent/tag count fields unused */
+} __packed;
+
+/* Trailing counts; cannot be a member after the flex array above */
+struct cxl_mbox_get_dc_config_tail {
+ __le32 num_extents_supported;
+ __le32 num_extents_available;
+ __le32 num_tags_supported;
+ __le32 num_tags_available;
+} __packed;
+#define CXL_DCD_BLOCK_LINE_SIZE 0x40
+
/* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */
struct cxl_mbox_set_timestamp_in {
__le64 timestamp;
@@ -812,9 +847,18 @@ enum {
int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox,
struct cxl_mbox_cmd *cmd);
int cxl_dev_state_identify(struct cxl_memdev_state *mds);
+
+struct cxl_dc_partition_info {
+ u64 start;
+ u64 size;
+};
+
+int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
+ struct cxl_dc_partition_info *dc_info);
int cxl_await_media_ready(struct cxl_dev_state *cxlds);
int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
+int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
u16 dvsec);
void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
@@ -828,6 +872,17 @@ void cxl_event_trace_record(struct cxl_memdev *cxlmd,
const uuid_t *uuid, union cxl_event *evt);
int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count);
int cxl_arm_dirty_shutdown(struct cxl_memdev_state *mds);
+
+static inline bool cxl_dcd_supported(struct cxl_memdev_state *mds)
+{
+ return mds->dcd_supported;
+}
+
+static inline void cxl_disable_dcd(struct cxl_memdev_state *mds)
+{
+ mds->dcd_supported = false;
+}
+
int cxl_set_timestamp(struct cxl_memdev_state *mds);
int cxl_poison_state_init(struct cxl_memdev_state *mds);
int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index c7c91e8dc51d..2fe9db4b3d86 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -868,6 +868,12 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (rc)
return rc;
+ if (cxl_dcd_supported(mds)) {
+ rc = cxl_configure_dcd(mds, &range_info);
+ if (rc)
+ cxl_disable_dcd(mds);
+ }
+
rc = cxl_dpa_setup(cxlds, &range_info);
if (rc)
return rc;
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index 802b143de83d..e07360849344 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -133,6 +133,7 @@ struct cxl_dpa_perf {
enum cxl_partition_mode {
CXL_PARTMODE_RAM,
CXL_PARTMODE_PMEM,
+ CXL_PARTMODE_DYNAMIC_RAM,
};
/**
@@ -147,7 +148,7 @@ struct cxl_dpa_partition {
enum cxl_partition_mode mode;
};
-#define CXL_NR_PARTITIONS_MAX 2
+#define CXL_NR_PARTITIONS_MAX 3
/**
* struct cxl_dev_state - The driver device state
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v16 2/8] cxl/mem: Read dynamic capacity configuration from the device
2026-10-10 22:54 ` [PATCH v16 2/8] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
@ 2026-10-12 11:47 ` Jonathan Cameron
2026-10-12 11:57 ` Jonathan Cameron
0 siblings, 1 reply; 17+ messages in thread
From: Jonathan Cameron @ 2026-10-12 11:47 UTC (permalink / raw)
To: Anisa Su
Cc: linux-cxl, nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Davidlohr Bueso, Ira Weiny, Vishal Verma, Fan Ni, Li Ming,
Benjamin Cheatham, Gregory Price, Richard Cheng, Anisa Su
On Sun, 11 Oct 2026 07:54:53 +0900
Anisa Su <anisa.su887@gmail.com> wrote:
> From: Ira Weiny <iweiny@kernel.org>
>
> Devices which support Dynamic Capacity (DC) are configured via mailbox
> commands. CXL r4.0 section 9.13.3 describes the use of the Get DC
> Configuration command in order to obtain DCD partition characteristics.
>
> Implement the DC mailbox commands as specified in CXL 4.0 section
> 8.2.10.9.9 (opcodes 48XXh) to read and store the DCD configuration
> information. Disable DCD if an invalid configuration is found.
>
> Initial enablement for Linux only supports one dynamic capacity
> partition. Read all the partitions the device reports but validate
> only the first, and configure it as 'dynamic ram'.
>
> The specification requires that volatile capacity starts at DPA 0 and
> pmem starts at the DPA immediately following it, but DC partitions only
> need to be 256MB aligned according to CXL r4.0 section 8.2.10.9.9.1
> Table 8-347. So a device could leave a gap between ram/pmem (static)
> capacity and its first DC partition, or between one DC partition and
> the next.
>
> However, Linux chooses not to support gaps between static and dynamic
> capacity, and requires the first DC partition to begin at the DPA
> immediately following static capacity.
>
> Based on an original patch by Navneet Singh.
>
> Signed-off-by: Ira Weiny <iweiny@kernel.org>
> Co-developed-by: Anisa Su <anisa.su@samsung.com>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
> Tested-by: Wonjae Lee <wj28.lee@samsung.com>
> Tested-by: Junhee Park <jh9934.park@samsung.com>
> Tested-by: Heesoo Kim <habil.kim@samsung.com>
>
A couple of things inline. Only one that matters I think is the
cleanup.h fragility / readability thing about constructors and
destructors needing to be near each other. That bit of guidance
came from a specific (and I think correct) comment from Linus
that he really wanted them together and if that meant declaring
the variables inline rather than in old school c style, then so be
it. That might be in category of things Dave could cleanup up whilst
applying if all else is ready but that's up to him.
Jonathan
> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> index 199bb986d674..72af23ba288e 100644
> --- a/drivers/cxl/core/mbox.c
> +++ b/drivers/cxl/core/mbox.c
> +/* Returns the number of partitions in dc_resp or -ERRNO */
> +static int cxl_get_dc_config(struct cxl_mailbox *mbox, u8 start_partition,
> + u8 partition_count,
> + struct cxl_mbox_get_dc_config_out *dc_resp,
> + size_t dc_resp_size)
> +{
> + struct cxl_mbox_get_dc_config_in get_dc = (struct cxl_mbox_get_dc_config_in) {
> + .partition_count = partition_count,
> + .start_partition_index = start_partition,
> + };
> + struct cxl_mbox_cmd mbox_cmd = (struct cxl_mbox_cmd) {
> + .opcode = CXL_MBOX_OP_GET_DC_CONFIG,
> + .payload_in = &get_dc,
> + .size_in = sizeof(get_dc),
> + .size_out = dc_resp_size,
> + .payload_out = dc_resp,
> + /* The device must return at least the fixed header */
> + .min_out = sizeof(*dc_resp),
> + };
> + size_t expected_sz;
> + int rc;
> +
> + rc = cxl_internal_send_cmd(mbox, &mbox_cmd);
> + if (rc < 0)
> + return rc;
> +
> + if (dc_resp->partitions_returned > partition_count) {
> + dev_err(mbox->host, "Device returned %u partitions, requested %u\n",
> + dc_resp->partitions_returned, partition_count);
> + return -EIO;
> + }
> +
> + /* The trailing extent/tag counts (CXL r4.0 Table 8-346) are not read */
> + expected_sz = struct_size(dc_resp, partition,
> + dc_resp->partitions_returned);
> +
> + if (mbox_cmd.size_out < expected_sz) {
> + dev_err(mbox->host,
> + "Payload size %zu less than expected %zu for %u partitions\n",
> + mbox_cmd.size_out,
> + expected_sz,
> + dc_resp->partitions_returned);
Not important, but if you do end up respinning, maybe don't have one parameter per line.
To me it doesn't really help with readability here.
> + return -EIO;
> + }
> +
> +/**
> + * cxl_dev_dc_identify() - Reads the dynamic capacity information from the
> + * device.
> + * @mbox: Mailbox to query
> + * @dc_info: The dynamic partition information to return
> + *
> + * Read every partition the device reports, but validate only the first:
> + * Linux maps partition 0 and nothing else, so a defect in capacity the
> + * driver never touches is not a reason to refuse the device dynamic
> + * capacity. The remaining partitions are read but not recorded.
> + *
> + * Return: 0 if identify was executed successfully, -ERRNO on error.
> + * On error, @dc_info is left unchanged.
> + */
> +int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
> + struct cxl_dc_partition_info *dc_info)
> +{
> + struct cxl_dc_partition_info partitions[CXL_MAX_DC_PARTITIONS] = { };
> + struct cxl_mbox_get_dc_config_out *dc_resp __free(kfree) = NULL;
See the cleanup.h guidance. This needs to move.
> + struct device *dev = mbox->host;
> + u8 avail_partitions = 0;
> + u8 start_partition;
> + u8 num_partitions;
> + u8 partition_count;
> + size_t dc_resp_size;
> +
> + /*
> + * Bound requested number of partitions by mailbox payload size. The
> + * 256 byte spec minimum, verified in cxl_pci_setup_mailbox(), keeps
> + * the subtraction below from underflowing.
> + */
> + partition_count = min(CXL_MAX_DC_PARTITIONS,
> + (mbox->payload_size - sizeof(*dc_resp) -
> + sizeof(struct cxl_mbox_get_dc_config_tail)) /
> + sizeof(struct cxl_dc_partition));
> + dc_resp_size = struct_size(dc_resp, partition, partition_count) +
> + sizeof(struct cxl_mbox_get_dc_config_tail);
> +
struct cxl_mbox_get_dc_config_out *dc_resp __free(kfree) =
kmalloc(dc_resp_size, GFP_KERNEL);
if (!dc_resp)
Maybe if everything else is fine, Dave can tweak this whilst applying.
star> + if (!dc_resp)
> + return -ENOMEM;
> +
> + start_partition = 0;
> + num_partitions = 0;
> + do {
> + int returned, rc;
> +
> + returned = cxl_get_dc_config(mbox, start_partition,
> + partition_count, dc_resp,
> + dc_resp_size);
> + if (returned < 0) {
> + dev_err(dev, "Failed to get DC config: %d\n", returned);
> + return returned;
> + }
> +
> + if (returned == 0) {
> + dev_err(dev,
> + "Device reported %u partitions available but returned none at index %u\n",
> + dc_resp->avail_partition_count, start_partition);
> + return -EIO;
> + }
> +
> + /* A DCD reports at least one partition (CXL r4.0 Table 8-346) */
> + if (dc_resp->avail_partition_count == 0) {
> + dev_err(dev, "Device reported no DC partitions\n");
> + return -EIO;
> + }
> +
> + avail_partitions = min(dc_resp->avail_partition_count,
> + CXL_MAX_DC_PARTITIONS);
> +
> + /*
> + * Only partition 0 is mapped, so it is the only one checked.
> + * The rest are read to complete the enumeration and dropped.
> + */
> + if (start_partition == 0) {
> + rc = cxl_dc_check(dev, &partitions[0],
> + &dc_resp->partition[0]);
> + if (rc)
> + return rc;
> + }
> +
> + num_partitions += returned;
> + start_partition = num_partitions;
I may be missing something subtle, but do start_partition and num_partitions ever
differ in value? Far as I can spot they are both only updated here. If they
change in later patches and this is churn reduction ignore this comment!
> +
> + } while (num_partitions < avail_partitions);
> +
> + /* Linux only supports the 1st partition; nothing to do if it is unavailable */
> + if (partitions[0].size == 0)
> + return -ENODEV;
> +
> + *dc_info = partitions[0];
> + dev_dbg(dev, "Returning partition 0 %#llx size %#llx\n",
> + dc_info->start, dc_info->size);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_dev_dc_identify, "CXL");
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v16 2/8] cxl/mem: Read dynamic capacity configuration from the device
2026-10-12 11:47 ` Jonathan Cameron
@ 2026-10-12 11:57 ` Jonathan Cameron
2026-10-12 16:53 ` Anisa Su
0 siblings, 1 reply; 17+ messages in thread
From: Jonathan Cameron @ 2026-10-12 11:57 UTC (permalink / raw)
To: Anisa Su
Cc: linux-cxl, nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Davidlohr Bueso, Ira Weiny, Vishal Verma, Fan Ni, Li Ming,
Benjamin Cheatham, Gregory Price, Richard Cheng, Anisa Su
On Mon, 12 Oct 2026 12:47:14 +0100
Jonathan Cameron <jic23@kernel.org> wrote:
> On Sun, 11 Oct 2026 07:54:53 +0900
> Anisa Su <anisa.su887@gmail.com> wrote:
>
> > From: Ira Weiny <iweiny@kernel.org>
> >
> > Devices which support Dynamic Capacity (DC) are configured via mailbox
> > commands. CXL r4.0 section 9.13.3 describes the use of the Get DC
> > Configuration command in order to obtain DCD partition characteristics.
> >
> > Implement the DC mailbox commands as specified in CXL 4.0 section
> > 8.2.10.9.9 (opcodes 48XXh) to read and store the DCD configuration
> > information. Disable DCD if an invalid configuration is found.
> >
> > Initial enablement for Linux only supports one dynamic capacity
> > partition. Read all the partitions the device reports but validate
> > only the first, and configure it as 'dynamic ram'.
> >
> > The specification requires that volatile capacity starts at DPA 0 and
> > pmem starts at the DPA immediately following it, but DC partitions only
> > need to be 256MB aligned according to CXL r4.0 section 8.2.10.9.9.1
> > Table 8-347. So a device could leave a gap between ram/pmem (static)
> > capacity and its first DC partition, or between one DC partition and
> > the next.
> >
> > However, Linux chooses not to support gaps between static and dynamic
> > capacity, and requires the first DC partition to begin at the DPA
> > immediately following static capacity.
> >
> > Based on an original patch by Navneet Singh.
> >
> > Signed-off-by: Ira Weiny <iweiny@kernel.org>
> > Co-developed-by: Anisa Su <anisa.su@samsung.com>
> > Signed-off-by: Anisa Su <anisa.su@samsung.com>
> > Tested-by: Wonjae Lee <wj28.lee@samsung.com>
> > Tested-by: Junhee Park <jh9934.park@samsung.com>
> > Tested-by: Heesoo Kim <habil.kim@samsung.com>
> >
>
> A couple of things inline. Only one that matters I think is the
> cleanup.h fragility / readability thing about constructors and
> destructors needing to be near each other. That bit of guidance
> came from a specific (and I think correct) comment from Linus
> that he really wanted them together and if that meant declaring
> the variables inline rather than in old school c style, then so be
> it. That might be in category of things Dave could cleanup up whilst
> applying if all else is ready but that's up to him.
>
Forgot to add, with that tweak
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
> Jonathan
>
>
> > diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> > index 199bb986d674..72af23ba288e 100644
> > --- a/drivers/cxl/core/mbox.c
> > +++ b/drivers/cxl/core/mbox.c
>
> > +/* Returns the number of partitions in dc_resp or -ERRNO */
> > +static int cxl_get_dc_config(struct cxl_mailbox *mbox, u8 start_partition,
> > + u8 partition_count,
> > + struct cxl_mbox_get_dc_config_out *dc_resp,
> > + size_t dc_resp_size)
> > +{
> > + struct cxl_mbox_get_dc_config_in get_dc = (struct cxl_mbox_get_dc_config_in) {
> > + .partition_count = partition_count,
> > + .start_partition_index = start_partition,
> > + };
> > + struct cxl_mbox_cmd mbox_cmd = (struct cxl_mbox_cmd) {
> > + .opcode = CXL_MBOX_OP_GET_DC_CONFIG,
> > + .payload_in = &get_dc,
> > + .size_in = sizeof(get_dc),
> > + .size_out = dc_resp_size,
> > + .payload_out = dc_resp,
> > + /* The device must return at least the fixed header */
> > + .min_out = sizeof(*dc_resp),
> > + };
> > + size_t expected_sz;
> > + int rc;
> > +
> > + rc = cxl_internal_send_cmd(mbox, &mbox_cmd);
> > + if (rc < 0)
> > + return rc;
> > +
> > + if (dc_resp->partitions_returned > partition_count) {
> > + dev_err(mbox->host, "Device returned %u partitions, requested %u\n",
> > + dc_resp->partitions_returned, partition_count);
> > + return -EIO;
> > + }
> > +
> > + /* The trailing extent/tag counts (CXL r4.0 Table 8-346) are not read */
> > + expected_sz = struct_size(dc_resp, partition,
> > + dc_resp->partitions_returned);
> > +
> > + if (mbox_cmd.size_out < expected_sz) {
> > + dev_err(mbox->host,
> > + "Payload size %zu less than expected %zu for %u partitions\n",
> > + mbox_cmd.size_out,
> > + expected_sz,
> > + dc_resp->partitions_returned);
>
> Not important, but if you do end up respinning, maybe don't have one parameter per line.
> To me it doesn't really help with readability here.
>
> > + return -EIO;
> > + }
> > +
> > +/**
> > + * cxl_dev_dc_identify() - Reads the dynamic capacity information from the
> > + * device.
> > + * @mbox: Mailbox to query
> > + * @dc_info: The dynamic partition information to return
> > + *
> > + * Read every partition the device reports, but validate only the first:
> > + * Linux maps partition 0 and nothing else, so a defect in capacity the
> > + * driver never touches is not a reason to refuse the device dynamic
> > + * capacity. The remaining partitions are read but not recorded.
> > + *
> > + * Return: 0 if identify was executed successfully, -ERRNO on error.
> > + * On error, @dc_info is left unchanged.
> > + */
> > +int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
> > + struct cxl_dc_partition_info *dc_info)
> > +{
> > + struct cxl_dc_partition_info partitions[CXL_MAX_DC_PARTITIONS] = { };
> > + struct cxl_mbox_get_dc_config_out *dc_resp __free(kfree) = NULL;
>
> See the cleanup.h guidance. This needs to move.
>
> > + struct device *dev = mbox->host;
> > + u8 avail_partitions = 0;
> > + u8 start_partition;
> > + u8 num_partitions;
> > + u8 partition_count;
> > + size_t dc_resp_size;
> > +
> > + /*
> > + * Bound requested number of partitions by mailbox payload size. The
> > + * 256 byte spec minimum, verified in cxl_pci_setup_mailbox(), keeps
> > + * the subtraction below from underflowing.
> > + */
> > + partition_count = min(CXL_MAX_DC_PARTITIONS,
> > + (mbox->payload_size - sizeof(*dc_resp) -
> > + sizeof(struct cxl_mbox_get_dc_config_tail)) /
> > + sizeof(struct cxl_dc_partition));
> > + dc_resp_size = struct_size(dc_resp, partition, partition_count) +
> > + sizeof(struct cxl_mbox_get_dc_config_tail);
> > +
>
> struct cxl_mbox_get_dc_config_out *dc_resp __free(kfree) =
> kmalloc(dc_resp_size, GFP_KERNEL);
> if (!dc_resp)
>
> Maybe if everything else is fine, Dave can tweak this whilst applying.
>
> star> + if (!dc_resp)
> > + return -ENOMEM;
> > +
> > + start_partition = 0;
> > + num_partitions = 0;
> > + do {
> > + int returned, rc;
> > +
> > + returned = cxl_get_dc_config(mbox, start_partition,
> > + partition_count, dc_resp,
> > + dc_resp_size);
> > + if (returned < 0) {
> > + dev_err(dev, "Failed to get DC config: %d\n", returned);
> > + return returned;
> > + }
> > +
> > + if (returned == 0) {
> > + dev_err(dev,
> > + "Device reported %u partitions available but returned none at index %u\n",
> > + dc_resp->avail_partition_count, start_partition);
> > + return -EIO;
> > + }
> > +
> > + /* A DCD reports at least one partition (CXL r4.0 Table 8-346) */
> > + if (dc_resp->avail_partition_count == 0) {
> > + dev_err(dev, "Device reported no DC partitions\n");
> > + return -EIO;
> > + }
> > +
> > + avail_partitions = min(dc_resp->avail_partition_count,
> > + CXL_MAX_DC_PARTITIONS);
> > +
> > + /*
> > + * Only partition 0 is mapped, so it is the only one checked.
> > + * The rest are read to complete the enumeration and dropped.
> > + */
> > + if (start_partition == 0) {
> > + rc = cxl_dc_check(dev, &partitions[0],
> > + &dc_resp->partition[0]);
> > + if (rc)
> > + return rc;
> > + }
> > +
> > + num_partitions += returned;
> > + start_partition = num_partitions;
>
> I may be missing something subtle, but do start_partition and num_partitions ever
> differ in value? Far as I can spot they are both only updated here. If they
> change in later patches and this is churn reduction ignore this comment!
>
>
> > +
> > + } while (num_partitions < avail_partitions);
> > +
> > + /* Linux only supports the 1st partition; nothing to do if it is unavailable */
> > + if (partitions[0].size == 0)
> > + return -ENODEV;
> > +
> > + *dc_info = partitions[0];
> > + dev_dbg(dev, "Returning partition 0 %#llx size %#llx\n",
> > + dc_info->start, dc_info->size);
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_NS_GPL(cxl_dev_dc_identify, "CXL");
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v16 2/8] cxl/mem: Read dynamic capacity configuration from the device
2026-10-12 11:57 ` Jonathan Cameron
@ 2026-10-12 16:53 ` Anisa Su
0 siblings, 0 replies; 17+ messages in thread
From: Anisa Su @ 2026-10-12 16:53 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Anisa Su, linux-cxl, nvdimm, linux-kernel, Dave Jiang,
Alison Schofield, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng
On Mon, Oct 12, 2026 at 12:57:56PM +0100, Jonathan Cameron wrote:
> On Mon, 12 Oct 2026 12:47:14 +0100
> Jonathan Cameron <jic23@kernel.org> wrote:
>
> > On Sun, 11 Oct 2026 07:54:53 +0900
> > Anisa Su <anisa.su887@gmail.com> wrote:
> >
> > > From: Ira Weiny <iweiny@kernel.org>
> > >
> > > Devices which support Dynamic Capacity (DC) are configured via mailbox
> > > commands. CXL r4.0 section 9.13.3 describes the use of the Get DC
> > > Configuration command in order to obtain DCD partition characteristics.
> > >
> > > Implement the DC mailbox commands as specified in CXL 4.0 section
> > > 8.2.10.9.9 (opcodes 48XXh) to read and store the DCD configuration
> > > information. Disable DCD if an invalid configuration is found.
> > >
> > > Initial enablement for Linux only supports one dynamic capacity
> > > partition. Read all the partitions the device reports but validate
> > > only the first, and configure it as 'dynamic ram'.
> > >
> > > The specification requires that volatile capacity starts at DPA 0 and
> > > pmem starts at the DPA immediately following it, but DC partitions only
> > > need to be 256MB aligned according to CXL r4.0 section 8.2.10.9.9.1
> > > Table 8-347. So a device could leave a gap between ram/pmem (static)
> > > capacity and its first DC partition, or between one DC partition and
> > > the next.
> > >
> > > However, Linux chooses not to support gaps between static and dynamic
> > > capacity, and requires the first DC partition to begin at the DPA
> > > immediately following static capacity.
> > >
> > > Based on an original patch by Navneet Singh.
> > >
> > > Signed-off-by: Ira Weiny <iweiny@kernel.org>
> > > Co-developed-by: Anisa Su <anisa.su@samsung.com>
> > > Signed-off-by: Anisa Su <anisa.su@samsung.com>
> > > Tested-by: Wonjae Lee <wj28.lee@samsung.com>
> > > Tested-by: Junhee Park <jh9934.park@samsung.com>
> > > Tested-by: Heesoo Kim <habil.kim@samsung.com>
> > >
> >
> > A couple of things inline. Only one that matters I think is the
> > cleanup.h fragility / readability thing about constructors and
> > destructors needing to be near each other. That bit of guidance
> > came from a specific (and I think correct) comment from Linus
> > that he really wanted them together and if that meant declaring
> > the variables inline rather than in old school c style, then so be
> > it. That might be in category of things Dave could cleanup up whilst
> > applying if all else is ready but that's up to him.
> >
> Forgot to add, with that tweak
>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
>
> > Jonathan
> >
> >
> > > diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> > > index 199bb986d674..72af23ba288e 100644
> > > --- a/drivers/cxl/core/mbox.c
> > > +++ b/drivers/cxl/core/mbox.c
> >
> > > +/* Returns the number of partitions in dc_resp or -ERRNO */
> > > +static int cxl_get_dc_config(struct cxl_mailbox *mbox, u8 start_partition,
> > > + u8 partition_count,
> > > + struct cxl_mbox_get_dc_config_out *dc_resp,
> > > + size_t dc_resp_size)
> > > +{
> > > + struct cxl_mbox_get_dc_config_in get_dc = (struct cxl_mbox_get_dc_config_in) {
> > > + .partition_count = partition_count,
> > > + .start_partition_index = start_partition,
> > > + };
> > > + struct cxl_mbox_cmd mbox_cmd = (struct cxl_mbox_cmd) {
> > > + .opcode = CXL_MBOX_OP_GET_DC_CONFIG,
> > > + .payload_in = &get_dc,
> > > + .size_in = sizeof(get_dc),
> > > + .size_out = dc_resp_size,
> > > + .payload_out = dc_resp,
> > > + /* The device must return at least the fixed header */
> > > + .min_out = sizeof(*dc_resp),
> > > + };
> > > + size_t expected_sz;
> > > + int rc;
> > > +
> > > + rc = cxl_internal_send_cmd(mbox, &mbox_cmd);
> > > + if (rc < 0)
> > > + return rc;
> > > +
> > > + if (dc_resp->partitions_returned > partition_count) {
> > > + dev_err(mbox->host, "Device returned %u partitions, requested %u\n",
> > > + dc_resp->partitions_returned, partition_count);
> > > + return -EIO;
> > > + }
> > > +
> > > + /* The trailing extent/tag counts (CXL r4.0 Table 8-346) are not read */
> > > + expected_sz = struct_size(dc_resp, partition,
> > > + dc_resp->partitions_returned);
> > > +
> > > + if (mbox_cmd.size_out < expected_sz) {
> > > + dev_err(mbox->host,
> > > + "Payload size %zu less than expected %zu for %u partitions\n",
> > > + mbox_cmd.size_out,
> > > + expected_sz,
> > > + dc_resp->partitions_returned);
> >
> > Not important, but if you do end up respinning, maybe don't have one parameter per line.
> > To me it doesn't really help with readability here.
> >
> > > + return -EIO;
> > > + }
> > > +
> > > +/**
> > > + * cxl_dev_dc_identify() - Reads the dynamic capacity information from the
> > > + * device.
> > > + * @mbox: Mailbox to query
> > > + * @dc_info: The dynamic partition information to return
> > > + *
> > > + * Read every partition the device reports, but validate only the first:
> > > + * Linux maps partition 0 and nothing else, so a defect in capacity the
> > > + * driver never touches is not a reason to refuse the device dynamic
> > > + * capacity. The remaining partitions are read but not recorded.
> > > + *
> > > + * Return: 0 if identify was executed successfully, -ERRNO on error.
> > > + * On error, @dc_info is left unchanged.
> > > + */
> > > +int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
> > > + struct cxl_dc_partition_info *dc_info)
> > > +{
> > > + struct cxl_dc_partition_info partitions[CXL_MAX_DC_PARTITIONS] = { };
> > > + struct cxl_mbox_get_dc_config_out *dc_resp __free(kfree) = NULL;
> >
> > See the cleanup.h guidance. This needs to move.
> >
> > > + struct device *dev = mbox->host;
> > > + u8 avail_partitions = 0;
> > > + u8 start_partition;
> > > + u8 num_partitions;
> > > + u8 partition_count;
> > > + size_t dc_resp_size;
> > > +
> > > + /*
> > > + * Bound requested number of partitions by mailbox payload size. The
> > > + * 256 byte spec minimum, verified in cxl_pci_setup_mailbox(), keeps
> > > + * the subtraction below from underflowing.
> > > + */
> > > + partition_count = min(CXL_MAX_DC_PARTITIONS,
> > > + (mbox->payload_size - sizeof(*dc_resp) -
> > > + sizeof(struct cxl_mbox_get_dc_config_tail)) /
> > > + sizeof(struct cxl_dc_partition));
> > > + dc_resp_size = struct_size(dc_resp, partition, partition_count) +
> > > + sizeof(struct cxl_mbox_get_dc_config_tail);
> > > +
> >
> > struct cxl_mbox_get_dc_config_out *dc_resp __free(kfree) =
> > kmalloc(dc_resp_size, GFP_KERNEL);
> > if (!dc_resp)
> >
> > Maybe if everything else is fine, Dave can tweak this whilst applying.
> >
> > star> + if (!dc_resp)
> > > + return -ENOMEM;
> > > +
> > > + start_partition = 0;
> > > + num_partitions = 0;
> > > + do {
> > > + int returned, rc;
> > > +
> > > + returned = cxl_get_dc_config(mbox, start_partition,
> > > + partition_count, dc_resp,
> > > + dc_resp_size);
> > > + if (returned < 0) {
> > > + dev_err(dev, "Failed to get DC config: %d\n", returned);
> > > + return returned;
> > > + }
> > > +
> > > + if (returned == 0) {
> > > + dev_err(dev,
> > > + "Device reported %u partitions available but returned none at index %u\n",
> > > + dc_resp->avail_partition_count, start_partition);
> > > + return -EIO;
> > > + }
> > > +
> > > + /* A DCD reports at least one partition (CXL r4.0 Table 8-346) */
> > > + if (dc_resp->avail_partition_count == 0) {
> > > + dev_err(dev, "Device reported no DC partitions\n");
> > > + return -EIO;
> > > + }
> > > +
> > > + avail_partitions = min(dc_resp->avail_partition_count,
> > > + CXL_MAX_DC_PARTITIONS);
> > > +
> > > + /*
> > > + * Only partition 0 is mapped, so it is the only one checked.
> > > + * The rest are read to complete the enumeration and dropped.
> > > + */
> > > + if (start_partition == 0) {
> > > + rc = cxl_dc_check(dev, &partitions[0],
> > > + &dc_resp->partition[0]);
> > > + if (rc)
> > > + return rc;
> > > + }
> > > +
> > > + num_partitions += returned;
> > > + start_partition = num_partitions;
> >
> > I may be missing something subtle, but do start_partition and num_partitions ever
> > differ in value? Far as I can spot they are both only updated here. If they
> > change in later patches and this is churn reduction ignore this comment!
> >
Oh oops. I didn't clean up properly.
We used to copy each partition into a local array in batches:
num_partitions += rc;
for (i = start_partition, j = 0; i < num_partitions; i++, j++) {
rc = cxl_dc_check(dev, partitions, i,
&dc_resp->partition[j]);
if (rc)
return rc;
}
start_partition = num_partitions;
But now we only validate the first, so it's no longer necessary. I removed the
loop but didn't clean up start_partitions/num_partitions.
Dave helped clean this up including the others you mentioned.
Thanks,
Anisa
> >
> > > +
> > > + } while (num_partitions < avail_partitions);
> > > +
> > > + /* Linux only supports the 1st partition; nothing to do if it is unavailable */
> > > + if (partitions[0].size == 0)
> > > + return -ENODEV;
> > > +
> > > + *dc_info = partitions[0];
> > > + dev_dbg(dev, "Returning partition 0 %#llx size %#llx\n",
> > > + dc_info->start, dc_info->size);
> > > +
> > > + return 0;
> > > +}
> > > +EXPORT_SYMBOL_NS_GPL(cxl_dev_dc_identify, "CXL");
> >
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v16 3/8] cxl/cdat: Gather DSMAS data for DCD partitions
2026-10-10 22:54 [PATCH v16 0/8] DCD Prep Series Anisa Su
2026-10-10 22:54 ` [PATCH v16 1/8] cxl/mbox: Flag support for Dynamic Capacity Devices (DCD) Anisa Su
2026-10-10 22:54 ` [PATCH v16 2/8] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
@ 2026-10-10 22:54 ` Anisa Su
2026-10-12 11:56 ` Jonathan Cameron
2026-10-10 22:54 ` [PATCH v16 4/8] cxl/events: Split event msgnum configuration from irq setup Anisa Su
` (6 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Anisa Su @ 2026-10-10 22:54 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
From: Ira Weiny <iweiny@kernel.org>
Additional DCD partition (AKA region) information is contained in the
DSMAS CDAT tables, including performance, shareable and read-only
attributes.
Match DCD partitions with DSMAS tables and store the meta data. A DCD
shall describe its DC partition in a DSMAS entry (CXL r4.0 9.13.3), so
if the CDAT is absent, fails to parse, or has no entry matching the DC
partition, disable DCD rather than run with unknown attributes.
DSLBIS is optional, but cxl_cdat_endpoint_process() treated zero DSLBIS
entries as a parse failure, which would now disable DCD on a device with
a valid DSMAS. Accept an empty DSLBIS, and skip DSMAS entries with no
DSLBIS coordinates.
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Co-developed-by: Anisa Su <anisa.su@samsung.com>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Tested-by: Wonjae Lee <wj28.lee@samsung.com>
Tested-by: Junhee Park <jh9934.park@samsung.com>
Tested-by: Heesoo Kim <habil.kim@samsung.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
---
Changes:
1. cdat.c: initialise dsmas_entry.qos_class to CXL_QOS_CLASS_INVALID so an
entry that is skipped (no DSLBIS) or whose QTG lookup fails no longer
reports qos_class 0, a valid class, through update_perf_entry().
[Sashiko]
2. mbox.c: handle > U8_MAX instead of an open-coded mask.
[Dave]
---
drivers/cxl/core/cdat.c | 99 ++++++++++++++++++++++++++++++++++-----
drivers/cxl/core/hdm.c | 1 +
drivers/cxl/core/mbox.c | 9 ++++
drivers/cxl/core/memdev.c | 17 ++++---
drivers/cxl/cxlmem.h | 11 +++++
include/cxl/cxl.h | 6 +++
6 files changed, 124 insertions(+), 19 deletions(-)
diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
index 5c9f07262513..ef04af813dbb 100644
--- a/drivers/cxl/core/cdat.c
+++ b/drivers/cxl/core/cdat.c
@@ -17,6 +17,8 @@ struct dsmas_entry {
struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX];
int entries;
int qos_class;
+ bool shareable;
+ bool read_only;
};
static u32 cdat_normalize(u16 entry, u64 base, u8 type)
@@ -73,7 +75,13 @@ static int cdat_dsmas_handler(union acpi_subtable_headers *header, void *arg,
if (!dent)
return -ENOMEM;
+ /* Stays invalid unless the QTG lookup assigns a class */
+ dent->qos_class = CXL_QOS_CLASS_INVALID;
dent->handle = dsmas->dsmad_handle;
+ /* Shareable is CDAT 1.03 and later, DSMAS Flags bit 3 */
+ dent->shareable = dsmas->flags & ACPI_CDAT_DSMAS_SHAREABLE;
+ /* Read Only is CDAT 1.04 and later, DSMAS Flags bit 6 */
+ dent->read_only = dsmas->flags & ACPI_CDAT_DSMAS_READ_ONLY;
dent->dpa_range.start = le64_to_cpu((__force __le64)dsmas->dpa_base_address);
dent->dpa_range.end = le64_to_cpu((__force __le64)dsmas->dpa_base_address) +
le64_to_cpu((__force __le64)dsmas->dpa_length) - 1;
@@ -188,9 +196,10 @@ static int cxl_cdat_endpoint_process(struct cxl_port *port,
if (rc)
return rc;
+ /* DSLBIS is optional; zero entries is not an error */
rc = cdat_table_parse(ACPI_CDAT_TYPE_DSLBIS, cdat_dslbis_handler,
dsmas_xa, port->cdat.table, port->cdat.length);
- return cdat_table_parse_output(rc);
+ return rc < 0 ? rc : 0;
}
static int cxl_port_perf_data_calculate(struct cxl_port *port,
@@ -219,6 +228,13 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
xa_for_each(dsmas_xa, index, dent) {
int qos_class;
+ /* No DSLBIS for this DSMAS; nothing to hand the QTG _DSM */
+ if (!dent->cdat_coord[ACCESS_COORDINATE_CPU].read_bandwidth &&
+ !dent->cdat_coord[ACCESS_COORDINATE_CPU].write_bandwidth &&
+ !dent->cdat_coord[ACCESS_COORDINATE_CPU].read_latency &&
+ !dent->cdat_coord[ACCESS_COORDINATE_CPU].write_latency)
+ continue;
+
cxl_coordinates_combine(dent->coord, dent->cdat_coord, ep_c);
dent->entries = 1;
rc = cxl_root->ops.qos_class(cxl_root,
@@ -255,35 +271,90 @@ static void update_perf_entry(struct device *dev, struct dsmas_entry *dent,
dent->coord[ACCESS_COORDINATE_CPU].write_latency);
}
-static void cxl_memdev_set_qos_class(struct cxl_dev_state *cxlds,
- struct xarray *dsmas_xa)
+/*
+ * A DCD shall describe its DC partition in a DSMAS entry (CXL r4.0 9.13.3).
+ * Without one the partition's attributes are unknown, so disable DCD.
+ */
+static void cxl_dcd_dsmas_missing(struct cxl_dev_state *cxlds, const char *why)
+{
+ struct cxl_memdev_state *mds;
+
+ if (cxlds->type != CXL_DEVTYPE_CLASSMEM)
+ return;
+
+ mds = to_cxl_memdev_state(cxlds);
+ if (!cxl_dcd_supported(mds) ||
+ !cxl_part_size(cxlds, CXL_PARTMODE_DYNAMIC_RAM))
+ return;
+
+ dev_warn(cxlds->dev, "DC partition has no valid DSMAS entry (%s), disabling DCD\n",
+ why);
+ cxl_disable_dcd(mds);
+}
+
+enum cxl_dsmas_apply {
+ CXL_DSMAS_APPLY_FLAGS, /* shareable etc.; no QTG data */
+ CXL_DSMAS_APPLY_FLAGS_PERF, /* perf coordinates and qos_class */
+};
+
+/*
+ * DSMAS flags such as shareable are properties of the CDAT entry and are
+ * applied regardless; perf data is applied only if the QTG lookup produced
+ * recommendations.
+ */
+static void cxl_memdev_apply_dsmas(struct cxl_dev_state *cxlds,
+ struct xarray *dsmas_xa,
+ enum cxl_dsmas_apply attrs)
{
struct device *dev = cxlds->dev;
struct dsmas_entry *dent;
+ bool dc_matched = false;
unsigned long index;
xa_for_each(dsmas_xa, index, dent) {
bool found = false;
for (int i = 0; i < cxlds->nr_partitions; i++) {
- struct resource *res = &cxlds->part[i].res;
+ struct cxl_dpa_partition *part = &cxlds->part[i];
struct range range = {
- .start = res->start,
- .end = res->end,
+ .start = part->res.start,
+ .end = part->res.end,
};
- if (range_contains(&range, &dent->dpa_range)) {
- update_perf_entry(dev, dent,
- &cxlds->part[i].perf);
- found = true;
+ if (!range_contains(&range, &dent->dpa_range))
+ continue;
+
+ found = true;
+ /*
+ * part->handle is from Get DC Config, dent->handle
+ * from the CDAT DSMAS entry.
+ */
+ if (part->mode == CXL_PARTMODE_DYNAMIC_RAM &&
+ dent->handle != part->handle) {
+ dev_warn(dev,
+ "DSMAD handle mismatch: %pra has %u, DSMAS %pra has %u\n",
+ &range, part->handle,
+ &dent->dpa_range, dent->handle);
break;
}
+
+ if (attrs == CXL_DSMAS_APPLY_FLAGS_PERF)
+ update_perf_entry(dev, dent, &part->perf);
+ if (part->mode == CXL_PARTMODE_DYNAMIC_RAM) {
+ part->shareable = dent->shareable;
+ part->read_only = dent->read_only;
+ dc_matched = true;
+ }
+ break;
}
if (!found)
dev_dbg(dev, "no partition for dsmas dpa: %pra\n",
&dent->dpa_range);
}
+
+ if (!dc_matched)
+ cxl_dcd_dsmas_missing(cxlds, "no matching entry");
}
static int match_cxlrd_qos_class(struct device *dev, void *data)
@@ -409,22 +480,26 @@ void cxl_endpoint_parse_cdat(struct cxl_port *port)
int rc;
xa_init(&__dsmas_xa);
- if (!port->cdat.table)
+ if (!port->cdat.table) {
+ cxl_dcd_dsmas_missing(cxlds, "no CDAT");
return;
+ }
rc = cxl_cdat_endpoint_process(port, dsmas_xa);
if (rc < 0) {
dev_dbg(&port->dev, "Failed to parse CDAT: %d\n", rc);
+ cxl_dcd_dsmas_missing(cxlds, "CDAT parse failed");
return;
}
rc = cxl_port_perf_data_calculate(port, dsmas_xa);
if (rc) {
dev_dbg(&port->dev, "Failed to do perf coord calculations.\n");
+ cxl_memdev_apply_dsmas(cxlds, dsmas_xa, CXL_DSMAS_APPLY_FLAGS);
return;
}
- cxl_memdev_set_qos_class(cxlds, dsmas_xa);
+ cxl_memdev_apply_dsmas(cxlds, dsmas_xa, CXL_DSMAS_APPLY_FLAGS_PERF);
cxl_qos_class_verify(cxlmd);
cxl_memdev_update_perf(cxlmd);
}
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 5fa2177cefcc..379540246333 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -486,6 +486,7 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
cxlds->part[i].perf.qos_class = CXL_QOS_CLASS_INVALID;
cxlds->part[i].mode = part->mode;
+ cxlds->part[i].handle = part->handle;
/* Require ordered + contiguous partitions */
if (i) {
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index 72af23ba288e..ae00e940d68c 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -1366,6 +1366,7 @@ static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part,
u64 decode_len = le64_to_cpu(dev_part->decode_length);
u64 blk_size = le64_to_cpu(dev_part->block_size);
u64 len = le64_to_cpu(dev_part->length);
+ u32 handle = le32_to_cpu(dev_part->dsmad_handle);
u64 size;
/*
@@ -1378,6 +1379,13 @@ static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part,
return 0;
}
+ /* The CDAT DSMAD handle this refers to is 8 bits */
+ if (handle > U8_MAX) {
+ dev_warn(dev, "DSMAD handle 0x%x exceeds the 8 bit CDAT DSMAD handle\n",
+ handle);
+ return -EINVAL;
+ }
+
/*
* Decode length is a count of 256M units, so a device reporting 2^36
* or more wraps.
@@ -1391,6 +1399,7 @@ static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part,
*part = (struct cxl_dc_partition_info) {
.start = le64_to_cpu(dev_part->base),
.size = size,
+ .handle = handle,
};
/*
diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
index 469767f1de70..71493231f5e5 100644
--- a/drivers/cxl/core/memdev.c
+++ b/drivers/cxl/core/memdev.c
@@ -594,7 +594,8 @@ bool is_cxl_memdev(const struct device *dev)
}
EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, "CXL");
-static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_partition_mode mode)
+static void add_part(struct cxl_dpa_info *info, u64 start, u64 size,
+ enum cxl_partition_mode mode, u8 handle)
{
int i = info->nr_partitions;
@@ -606,6 +607,7 @@ static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_pa
.end = start + size - 1,
};
info->part[i].mode = mode;
+ info->part[i].handle = handle;
info->nr_partitions++;
}
@@ -623,9 +625,9 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
info->size = mds->total_bytes;
if (mds->partition_align_bytes == 0) {
- add_part(info, 0, mds->volatile_only_bytes, CXL_PARTMODE_RAM);
+ add_part(info, 0, mds->volatile_only_bytes, CXL_PARTMODE_RAM, 0);
add_part(info, mds->volatile_only_bytes,
- mds->persistent_only_bytes, CXL_PARTMODE_PMEM);
+ mds->persistent_only_bytes, CXL_PARTMODE_PMEM, 0);
return 0;
}
@@ -635,9 +637,9 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
return rc;
}
- add_part(info, 0, mds->active_volatile_bytes, CXL_PARTMODE_RAM);
+ add_part(info, 0, mds->active_volatile_bytes, CXL_PARTMODE_RAM, 0);
add_part(info, mds->active_volatile_bytes, mds->active_persistent_bytes,
- CXL_PARTMODE_PMEM);
+ CXL_PARTMODE_PMEM, 0);
return 0;
}
@@ -691,7 +693,8 @@ int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
info->size = dc_end;
dev_dbg(dev, "Adding dynamic ram partition; %#llx size %#llx\n",
dc_info.start, dc_info.size);
- add_part(info, dc_info.start, dc_info.size, CXL_PARTMODE_DYNAMIC_RAM);
+ add_part(info, dc_info.start, dc_info.size, CXL_PARTMODE_DYNAMIC_RAM,
+ dc_info.handle);
return 0;
}
@@ -709,7 +712,7 @@ int cxl_set_capacity(struct cxl_dev_state *cxlds, u64 capacity)
.size = capacity,
};
- add_part(&range_info, 0, capacity, CXL_PARTMODE_RAM);
+ add_part(&range_info, 0, capacity, CXL_PARTMODE_RAM, 0);
return cxl_dpa_setup(cxlds, &range_info);
}
EXPORT_SYMBOL_NS_GPL(cxl_set_capacity, "CXL");
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 4fac65dbb808..b539b5a5c829 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -140,6 +140,7 @@ struct cxl_dpa_info {
struct cxl_dpa_part_info {
struct range range;
enum cxl_partition_mode mode;
+ u8 handle;
} part[CXL_NR_PARTITIONS_MAX];
int nr_partitions;
};
@@ -421,6 +422,15 @@ static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
return 0;
}
+static inline resource_size_t cxl_part_size(struct cxl_dev_state *cxlds,
+ enum cxl_partition_mode mode)
+{
+ for (int i = 0; i < cxlds->nr_partitions; i++)
+ if (cxlds->part[i].mode == mode)
+ return resource_size(&cxlds->part[i].res);
+ return 0;
+}
+
static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox)
{
return dev_get_drvdata(cxl_mbox->host);
@@ -851,6 +861,7 @@ int cxl_dev_state_identify(struct cxl_memdev_state *mds);
struct cxl_dc_partition_info {
u64 start;
u64 size;
+ u8 handle;
};
int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index e07360849344..728decda57fd 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -141,11 +141,17 @@ enum cxl_partition_mode {
* @res: shortcut to the partition in the DPA resource tree (cxlds->dpa_res)
* @perf: performance attributes of the partition from CDAT
* @mode: operation mode for the DPA capacity, e.g. ram, pmem, dynamic...
+ * @handle: DSMAS handle that represents this partition
+ * @shareable: Is the partition shareable (from its CDAT DSMAS entry)
+ * @read_only: Is the partition read-only (from its CDAT DSMAS entry)
*/
struct cxl_dpa_partition {
struct resource res;
struct cxl_dpa_perf perf;
enum cxl_partition_mode mode;
+ u8 handle;
+ bool shareable;
+ bool read_only;
};
#define CXL_NR_PARTITIONS_MAX 3
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v16 3/8] cxl/cdat: Gather DSMAS data for DCD partitions
2026-10-10 22:54 ` [PATCH v16 3/8] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
@ 2026-10-12 11:56 ` Jonathan Cameron
0 siblings, 0 replies; 17+ messages in thread
From: Jonathan Cameron @ 2026-10-12 11:56 UTC (permalink / raw)
To: Anisa Su
Cc: linux-cxl, nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Davidlohr Bueso, Ira Weiny, Vishal Verma, Fan Ni, Li Ming,
Benjamin Cheatham, Gregory Price, Richard Cheng, Anisa Su
On Sun, 11 Oct 2026 07:54:54 +0900
Anisa Su <anisa.su887@gmail.com> wrote:
> From: Ira Weiny <iweiny@kernel.org>
>
> Additional DCD partition (AKA region) information is contained in the
> DSMAS CDAT tables, including performance, shareable and read-only
> attributes.
>
> Match DCD partitions with DSMAS tables and store the meta data. A DCD
> shall describe its DC partition in a DSMAS entry (CXL r4.0 9.13.3), so
> if the CDAT is absent, fails to parse, or has no entry matching the DC
> partition, disable DCD rather than run with unknown attributes.
>
> DSLBIS is optional, but cxl_cdat_endpoint_process() treated zero DSLBIS
> entries as a parse failure, which would now disable DCD on a device with
> a valid DSMAS. Accept an empty DSLBIS, and skip DSMAS entries with no
> DSLBIS coordinates.
>
> Signed-off-by: Ira Weiny <iweiny@kernel.org>
> Co-developed-by: Anisa Su <anisa.su@samsung.com>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
> Tested-by: Wonjae Lee <wj28.lee@samsung.com>
> Tested-by: Junhee Park <jh9934.park@samsung.com>
> Tested-by: Heesoo Kim <habil.kim@samsung.com>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v16 4/8] cxl/events: Split event msgnum configuration from irq setup
2026-10-10 22:54 [PATCH v16 0/8] DCD Prep Series Anisa Su
` (2 preceding siblings ...)
2026-10-10 22:54 ` [PATCH v16 3/8] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
@ 2026-10-10 22:54 ` Anisa Su
2026-10-10 22:54 ` [PATCH v16 5/8] cxl/pci: Factor out interrupt policy check Anisa Su
` (5 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Anisa Su @ 2026-10-10 22:54 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
From: Ira Weiny <iweiny@kernel.org>
Dynamic Capacity Devices (DCD) require event interrupts to process
memory addition or removal. BIOS may have control over non-DCD event
processing. DCD interrupt configuration needs to be separate from
memory event interrupt configuration.
Split cxl_event_config_msgnums() from irq setup in preparation for
separate DCD interrupts configuration.
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Tested-by: Wonjae Lee <wj28.lee@samsung.com>
Tested-by: Junhee Park <jh9934.park@samsung.com>
Tested-by: Heesoo Kim <habil.kim@samsung.com>
Reviewed-by: Jonathan Cameron <jic23@kernel.org>
Reviewed-by: Fan Ni <nifan.cxl@gmail.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Richard Cheng <icheng@nvidia.com>
---
drivers/cxl/pci.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 2fe9db4b3d86..4867657f5526 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -600,35 +600,31 @@ static int cxl_event_config_msgnums(struct cxl_memdev_state *mds,
return cxl_event_get_int_policy(mds, policy);
}
-static int cxl_event_irqsetup(struct cxl_memdev_state *mds)
+static int cxl_event_irqsetup(struct cxl_memdev_state *mds,
+ struct cxl_event_interrupt_policy *policy)
{
struct cxl_dev_state *cxlds = &mds->cxlds;
- struct cxl_event_interrupt_policy policy;
int rc;
- rc = cxl_event_config_msgnums(mds, &policy);
- if (rc)
- return rc;
-
- rc = cxl_event_req_irq(cxlds, policy.info_settings);
+ rc = cxl_event_req_irq(cxlds, policy->info_settings);
if (rc) {
dev_err(cxlds->dev, "Failed to get interrupt for event Info log\n");
return rc;
}
- rc = cxl_event_req_irq(cxlds, policy.warn_settings);
+ rc = cxl_event_req_irq(cxlds, policy->warn_settings);
if (rc) {
dev_err(cxlds->dev, "Failed to get interrupt for event Warn log\n");
return rc;
}
- rc = cxl_event_req_irq(cxlds, policy.failure_settings);
+ rc = cxl_event_req_irq(cxlds, policy->failure_settings);
if (rc) {
dev_err(cxlds->dev, "Failed to get interrupt for event Failure log\n");
return rc;
}
- rc = cxl_event_req_irq(cxlds, policy.fatal_settings);
+ rc = cxl_event_req_irq(cxlds, policy->fatal_settings);
if (rc) {
dev_err(cxlds->dev, "Failed to get interrupt for event Fatal log\n");
return rc;
@@ -675,11 +671,15 @@ static int cxl_event_config(struct pci_host_bridge *host_bridge,
return -EBUSY;
}
+ rc = cxl_event_config_msgnums(mds, &policy);
+ if (rc)
+ return rc;
+
rc = cxl_mem_alloc_event_buf(mds);
if (rc)
return rc;
- rc = cxl_event_irqsetup(mds);
+ rc = cxl_event_irqsetup(mds, &policy);
if (rc)
return rc;
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v16 5/8] cxl/pci: Factor out interrupt policy check
2026-10-10 22:54 [PATCH v16 0/8] DCD Prep Series Anisa Su
` (3 preceding siblings ...)
2026-10-10 22:54 ` [PATCH v16 4/8] cxl/events: Split event msgnum configuration from irq setup Anisa Su
@ 2026-10-10 22:54 ` Anisa Su
2026-10-10 22:54 ` [PATCH v16 6/8] cxl/mem: Configure dynamic capacity interrupts Anisa Su
` (4 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Anisa Su @ 2026-10-10 22:54 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
From: Ira Weiny <iweiny@kernel.org>
Dynamic Capacity Devices (DCD) require event interrupts to process
memory addition or removal. BIOS may have control over non-DCD event
processing. DCD interrupt configuration needs to be separate from
memory event interrupt configuration.
Factor out check for firmware ownership of memory event logs.
Link: https://lore.kernel.org/all/663922b475e50_d54d72945b@dwillia2-xfh.jf.intel.com.notmuch/ [1]
Suggested-by: Dan Williams <djbw@kernel.org>
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Tested-by: Wonjae Lee <wj28.lee@samsung.com>
Tested-by: Junhee Park <jh9934.park@samsung.com>
Tested-by: Heesoo Kim <habil.kim@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jic23@kernel.org>
Reviewed-by: Fan Ni <nifan.cxl@gmail.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Richard Cheng <icheng@nvidia.com>
---
drivers/cxl/pci.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 4867657f5526..7b754af2168d 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -640,6 +640,14 @@ static bool cxl_event_int_is_fw(u8 setting)
return mode == CXL_INT_FW;
}
+static bool cxl_event_fw_owns_mem_logs(struct cxl_event_interrupt_policy *policy)
+{
+ return cxl_event_int_is_fw(policy->info_settings) ||
+ cxl_event_int_is_fw(policy->warn_settings) ||
+ cxl_event_int_is_fw(policy->failure_settings) ||
+ cxl_event_int_is_fw(policy->fatal_settings);
+}
+
static int cxl_event_config(struct pci_host_bridge *host_bridge,
struct cxl_memdev_state *mds, bool irq_avail)
{
@@ -662,10 +670,7 @@ static int cxl_event_config(struct pci_host_bridge *host_bridge,
if (rc)
return rc;
- if (cxl_event_int_is_fw(policy.info_settings) ||
- cxl_event_int_is_fw(policy.warn_settings) ||
- cxl_event_int_is_fw(policy.failure_settings) ||
- cxl_event_int_is_fw(policy.fatal_settings)) {
+ if (cxl_event_fw_owns_mem_logs(&policy)) {
dev_err(mds->cxlds.dev,
"FW still in control of Event Logs despite _OSC settings\n");
return -EBUSY;
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v16 6/8] cxl/mem: Configure dynamic capacity interrupts
2026-10-10 22:54 [PATCH v16 0/8] DCD Prep Series Anisa Su
` (4 preceding siblings ...)
2026-10-10 22:54 ` [PATCH v16 5/8] cxl/pci: Factor out interrupt policy check Anisa Su
@ 2026-10-10 22:54 ` Anisa Su
2026-10-12 14:05 ` Jonathan Cameron
2026-10-10 22:54 ` [PATCH v16 7/8] cxl/core: Enforce partition order/simplify partition calls Anisa Su
` (3 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Anisa Su @ 2026-10-10 22:54 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
From: Ira Weiny <iweiny@kernel.org>
Dynamic Capacity Devices (DCD) support extent change notifications
through the event log mechanism. The interrupt mailbox commands were
extended in CXL 3.1 to support these notifications. Firmware can't
configure DCD events to be FW controlled but can retain control of
memory events.
Configure DCD event log interrupts on devices supporting dynamic
capacity. Disable DCD if interrupts are not supported.
The DCD event log is not drained here. cxl_event_drain_mask() reports
only the logs the driver can service, and the DCD bit is added by
the patch introducing DCD event handling. Until then a DCD interrupt
wakes the event thread, which finds no log it owns and returns.
Care is taken to preserve the interrupt policy set by the FW if FW first
has been selected by the BIOS.
Based on an original patch by Navneet Singh.
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Co-developed-by: Anisa Su <anisa.su@samsung.com>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Tested-by: Wonjae Lee <wj28.lee@samsung.com>
Tested-by: Junhee Park <jh9934.park@samsung.com>
Tested-by: Heesoo Kim <habil.kim@samsung.com>
---
Changes:
1. When the DCD vector cannot be requested, clear dcd_settings on the
device with Set Event Interrupt Policy as well as disabling DCD on
the host, so the device does not keep signalling a vector with no
handler. The Set Event Interrupt Policy command moves out of
cxl_event_config_msgnums() into a new helper,
cxl_event_set_int_policy(), so cxl_irqsetup() can issue it too.
[Richard]
---
drivers/cxl/cxl.h | 14 ++-
drivers/cxl/cxlmem.h | 2 +
drivers/cxl/pci.c | 174 +++++++++++++++++++++++++++++------
tools/testing/cxl/test/mem.c | 2 +-
4 files changed, 156 insertions(+), 36 deletions(-)
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index cab8ce39f465..15356d25369d 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -192,11 +192,15 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
#define CXLDEV_EVENT_STATUS_WARN BIT(1)
#define CXLDEV_EVENT_STATUS_FAIL BIT(2)
#define CXLDEV_EVENT_STATUS_FATAL BIT(3)
-
-#define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \
- CXLDEV_EVENT_STATUS_WARN | \
- CXLDEV_EVENT_STATUS_FAIL | \
- CXLDEV_EVENT_STATUS_FATAL)
+#define CXLDEV_EVENT_STATUS_DCD BIT(4)
+/*
+ * Logs whose ownership follows native_cxl_error; the DCD log is always
+ * OS owned.
+ */
+#define CXLDEV_EVENT_STATUS_STANDARD_LOGS (CXLDEV_EVENT_STATUS_INFO | \
+ CXLDEV_EVENT_STATUS_WARN | \
+ CXLDEV_EVENT_STATUS_FAIL | \
+ CXLDEV_EVENT_STATUS_FATAL)
/* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */
#define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0)
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index b539b5a5c829..bac7e1ac715f 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -240,7 +240,9 @@ struct cxl_event_interrupt_policy {
u8 warn_settings;
u8 failure_settings;
u8 fatal_settings;
+ u8 dcd_settings;
} __packed;
+#define CXL_EVENT_INT_POLICY_BASE_SIZE 4 /* info, warn, failure, fatal */
/**
* struct cxl_event_state - Event log driver state
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 7b754af2168d..1d94e9ebb1a2 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -510,11 +510,22 @@ static bool cxl_alloc_irq_vectors(struct pci_dev *pdev)
return true;
}
+/* Event logs the driver drains: standard logs when native_cxl */
+static u32 cxl_event_drain_mask(struct pci_host_bridge *host_bridge)
+{
+ if (host_bridge->native_cxl_error)
+ return CXLDEV_EVENT_STATUS_STANDARD_LOGS;
+ return 0;
+}
+
static irqreturn_t cxl_event_thread(int irq, void *id)
{
struct cxl_dev_id *dev_id = id;
struct cxl_dev_state *cxlds = dev_id->cxlds;
struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
+ struct pci_host_bridge *host_bridge =
+ pci_find_host_bridge(to_pci_dev(cxlds->dev)->bus);
+ u32 mask = cxl_event_drain_mask(host_bridge);
u32 status;
do {
@@ -523,8 +534,8 @@ static irqreturn_t cxl_event_thread(int irq, void *id)
* ignore the reserved upper 32 bits
*/
status = readl(cxlds->regs.status + CXLDEV_DEV_EVENT_STATUS_OFFSET);
- /* Ignore logs unknown to the driver */
- status &= CXLDEV_EVENT_STATUS_ALL;
+ /* Ignore logs unknown to the driver or owned by BIOS */
+ status &= mask;
if (!status)
break;
cxl_mem_get_event_records(mds, status);
@@ -551,53 +562,81 @@ static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting)
}
static int cxl_event_get_int_policy(struct cxl_memdev_state *mds,
- struct cxl_event_interrupt_policy *policy)
+ struct cxl_event_interrupt_policy *policy,
+ size_t *policy_size)
{
struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
struct cxl_mbox_cmd mbox_cmd = {
.opcode = CXL_MBOX_OP_GET_EVT_INT_POLICY,
.payload_out = policy,
.size_out = sizeof(*policy),
+ /* CXL 2.0 firmware omits dcd_settings; accept the shorter reply */
+ .min_out = CXL_EVENT_INT_POLICY_BASE_SIZE,
};
int rc;
rc = cxl_internal_send_cmd(cxl_mbox, &mbox_cmd);
- if (rc < 0)
+ if (rc < 0) {
dev_err(mds->cxlds.dev,
"Failed to get event interrupt policy : %d", rc);
+ return rc;
+ }
+ if (policy_size)
+ *policy_size = mbox_cmd.size_out;
return rc;
}
-static int cxl_event_config_msgnums(struct cxl_memdev_state *mds,
- struct cxl_event_interrupt_policy *policy)
+static int cxl_event_set_int_policy(struct cxl_memdev_state *mds,
+ struct cxl_event_interrupt_policy *policy,
+ size_t policy_size)
{
struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
- struct cxl_mbox_cmd mbox_cmd;
- int rc;
-
- *policy = (struct cxl_event_interrupt_policy) {
- .info_settings = CXL_INT_MSI_MSIX,
- .warn_settings = CXL_INT_MSI_MSIX,
- .failure_settings = CXL_INT_MSI_MSIX,
- .fatal_settings = CXL_INT_MSI_MSIX,
- };
-
- mbox_cmd = (struct cxl_mbox_cmd) {
+ struct cxl_mbox_cmd mbox_cmd = {
.opcode = CXL_MBOX_OP_SET_EVT_INT_POLICY,
.payload_in = policy,
- .size_in = sizeof(*policy),
+ .size_in = policy_size,
};
+ int rc;
rc = cxl_internal_send_cmd(cxl_mbox, &mbox_cmd);
- if (rc < 0) {
+ if (rc < 0)
dev_err(mds->cxlds.dev, "Failed to set event interrupt policy : %d",
rc);
- return rc;
+ return rc;
+}
+
+static int cxl_event_config_msgnums(struct cxl_memdev_state *mds,
+ struct cxl_event_interrupt_policy *policy,
+ bool native_cxl, size_t policy_size)
+{
+ int rc;
+
+ /* memory event policy is left if FW has control */
+ if (native_cxl) {
+ *policy = (struct cxl_event_interrupt_policy) {
+ .info_settings = CXL_INT_MSI_MSIX,
+ .warn_settings = CXL_INT_MSI_MSIX,
+ .failure_settings = CXL_INT_MSI_MSIX,
+ .fatal_settings = CXL_INT_MSI_MSIX,
+ .dcd_settings = 0,
+ };
}
+ /*
+ * A CXL 3.0+ device can carry dcd_settings field without DCD command
+ * support, so size the request by the device's policy_size and only
+ * enable the DCD interrupt when DCD commands are supported.
+ */
+ if (cxl_dcd_supported(mds))
+ policy->dcd_settings = CXL_INT_MSI_MSIX;
+
+ rc = cxl_event_set_int_policy(mds, policy, policy_size);
+ if (rc)
+ return rc;
+
/* Retrieve final interrupt settings */
- return cxl_event_get_int_policy(mds, policy);
+ return cxl_event_get_int_policy(mds, policy, NULL);
}
static int cxl_event_irqsetup(struct cxl_memdev_state *mds,
@@ -633,6 +672,37 @@ static int cxl_event_irqsetup(struct cxl_memdev_state *mds,
return 0;
}
+static int cxl_irqsetup(struct cxl_memdev_state *mds,
+ struct cxl_event_interrupt_policy *policy,
+ bool native_cxl, size_t policy_size)
+{
+ struct cxl_dev_state *cxlds = &mds->cxlds;
+ int rc;
+
+ if (native_cxl) {
+ rc = cxl_event_irqsetup(mds, policy);
+ if (rc)
+ return rc;
+ }
+
+ if (cxl_dcd_supported(mds)) {
+ rc = cxl_event_req_irq(cxlds, policy->dcd_settings);
+ if (rc) {
+ dev_err(cxlds->dev, "Failed to get interrupt for DCD event log\n");
+ cxl_disable_dcd(mds);
+ /* No handler will service the DCD vector; tell the device */
+ policy->dcd_settings = CXL_INT_NONE;
+ rc = cxl_event_set_int_policy(mds, policy, policy_size);
+ if (rc)
+ dev_warn(cxlds->dev,
+ "DCD disabled but its interrupt policy could not be cleared: %d\n",
+ rc);
+ }
+ }
+
+ return 0;
+}
+
static bool cxl_event_int_is_fw(u8 setting)
{
u8 mode = FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting);
@@ -651,46 +721,90 @@ static bool cxl_event_fw_owns_mem_logs(struct cxl_event_interrupt_policy *policy
static int cxl_event_config(struct pci_host_bridge *host_bridge,
struct cxl_memdev_state *mds, bool irq_avail)
{
- struct cxl_event_interrupt_policy policy;
+ struct cxl_event_interrupt_policy policy = { 0 };
+ bool native_cxl = host_bridge->native_cxl_error;
+ size_t policy_size;
+ u32 mask;
int rc;
/*
* When BIOS maintains CXL error reporting control, it will process
* event records. Only one agent can do so.
+ *
+ * If BIOS has control of events and DCD is not supported skip event
+ * configuration.
*/
- if (!host_bridge->native_cxl_error)
+ if (!native_cxl && !cxl_dcd_supported(mds))
return 0;
if (!irq_avail) {
dev_info(mds->cxlds.dev, "No interrupt support, disable event processing.\n");
+ if (cxl_dcd_supported(mds)) {
+ dev_info(mds->cxlds.dev, "DCD requires interrupts, disable DCD\n");
+ cxl_disable_dcd(mds);
+ }
return 0;
}
- rc = cxl_event_get_int_policy(mds, &policy);
+ rc = cxl_event_get_int_policy(mds, &policy, &policy_size);
if (rc)
- return rc;
+ goto err;
+
+ /*
+ * dcd_settings cannot be sent to a device whose policy is too short
+ * to hold it, so the device would never accept the setting
+ * cxl_irqsetup() arms the DCD interrupt with.
+ */
+ if (cxl_dcd_supported(mds) && policy_size < sizeof(policy)) {
+ dev_warn(mds->cxlds.dev,
+ "DCD supported but interrupt policy is only %zu bytes\n",
+ policy_size);
+ cxl_disable_dcd(mds);
+ /* DCD was the only reason to be here */
+ if (!native_cxl)
+ return 0;
+ }
- if (cxl_event_fw_owns_mem_logs(&policy)) {
+ if (native_cxl && cxl_event_fw_owns_mem_logs(&policy)) {
dev_err(mds->cxlds.dev,
"FW still in control of Event Logs despite _OSC settings\n");
return -EBUSY;
}
- rc = cxl_event_config_msgnums(mds, &policy);
+ rc = cxl_event_config_msgnums(mds, &policy, native_cxl, policy_size);
if (rc)
- return rc;
+ goto err;
rc = cxl_mem_alloc_event_buf(mds);
if (rc)
return rc;
- rc = cxl_event_irqsetup(mds, &policy);
+ rc = cxl_irqsetup(mds, &policy, native_cxl, policy_size);
if (rc)
return rc;
- cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_ALL);
+ mask = cxl_event_drain_mask(host_bridge);
+ if (mask)
+ cxl_mem_get_event_records(mds, mask);
+
+ dev_dbg(mds->cxlds.dev, "Event config : %s DCD %s\n",
+ native_cxl ? "OS" : "BIOS",
+ cxl_dcd_supported(mds) ? "supported" : "not supported");
return 0;
+
+err:
+ /*
+ * Failed to Get/Set interrupt policy for DCD while BIOS owns the
+ * other logs. Disable DCD and continue.
+ */
+ if (!native_cxl) {
+ dev_warn(mds->cxlds.dev,
+ "Event interrupt policy failed (%d), disabling DCD\n", rc);
+ cxl_disable_dcd(mds);
+ return 0;
+ }
+ return rc;
}
static int cxl_pci_type3_init_mailbox(struct cxl_dev_state *cxlds)
diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
index 7b756000a1a6..c740372bdaaa 100644
--- a/tools/testing/cxl/test/mem.c
+++ b/tools/testing/cxl/test/mem.c
@@ -1818,7 +1818,7 @@ static int cxl_mock_mem_probe(struct platform_device *pdev)
if (rc)
dev_dbg(dev, "No CXL FWCTL setup\n");
- cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_ALL);
+ cxl_mem_get_event_records(mds, CXLDEV_EVENT_STATUS_STANDARD_LOGS);
cxl_mock_test_feat_init(mdata);
return 0;
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v16 6/8] cxl/mem: Configure dynamic capacity interrupts
2026-10-10 22:54 ` [PATCH v16 6/8] cxl/mem: Configure dynamic capacity interrupts Anisa Su
@ 2026-10-12 14:05 ` Jonathan Cameron
0 siblings, 0 replies; 17+ messages in thread
From: Jonathan Cameron @ 2026-10-12 14:05 UTC (permalink / raw)
To: Anisa Su
Cc: linux-cxl, nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Davidlohr Bueso, Ira Weiny, Vishal Verma, Fan Ni, Li Ming,
Benjamin Cheatham, Gregory Price, Richard Cheng, Anisa Su
On Sun, 11 Oct 2026 07:54:57 +0900
Anisa Su <anisa.su887@gmail.com> wrote:
> From: Ira Weiny <iweiny@kernel.org>
>
> Dynamic Capacity Devices (DCD) support extent change notifications
> through the event log mechanism. The interrupt mailbox commands were
> extended in CXL 3.1 to support these notifications. Firmware can't
> configure DCD events to be FW controlled but can retain control of
> memory events.
>
> Configure DCD event log interrupts on devices supporting dynamic
> capacity. Disable DCD if interrupts are not supported.
>
> The DCD event log is not drained here. cxl_event_drain_mask() reports
> only the logs the driver can service, and the DCD bit is added by
> the patch introducing DCD event handling. Until then a DCD interrupt
> wakes the event thread, which finds no log it owns and returns.
>
> Care is taken to preserve the interrupt policy set by the FW if FW first
> has been selected by the BIOS.
>
> Based on an original patch by Navneet Singh.
>
> Signed-off-by: Ira Weiny <iweiny@kernel.org>
> Co-developed-by: Anisa Su <anisa.su@samsung.com>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
> Tested-by: Wonjae Lee <wj28.lee@samsung.com>
> Tested-by: Junhee Park <jh9934.park@samsung.com>
> Tested-by: Heesoo Kim <habil.kim@samsung.com>
>
One really minor thing below. Up to you on whether you change
it even if you do respin!
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
> static bool cxl_event_int_is_fw(u8 setting)
> {
> u8 mode = FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting);
> @@ -651,46 +721,90 @@ static bool cxl_event_fw_owns_mem_logs(struct cxl_event_interrupt_policy *policy
> static int cxl_event_config(struct pci_host_bridge *host_bridge,
> struct cxl_memdev_state *mds, bool irq_avail)
> {
> - struct cxl_event_interrupt_policy policy;
> + struct cxl_event_interrupt_policy policy = { 0 };
Trivial but in earlier patch you used {}; for the bitmap.
They are equivalent (with modern compilers + the options the kernel uses)
but consistency would nice if you do respin. Not major enough to justify
doing that though! I think we already have a mix in CXL so this isn't
really making it worse.
Jonathan
> + bool native_cxl = host_bridge->native_cxl_error;
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v16 7/8] cxl/core: Enforce partition order/simplify partition calls
2026-10-10 22:54 [PATCH v16 0/8] DCD Prep Series Anisa Su
` (5 preceding siblings ...)
2026-10-10 22:54 ` [PATCH v16 6/8] cxl/mem: Configure dynamic capacity interrupts Anisa Su
@ 2026-10-10 22:54 ` Anisa Su
2026-10-10 22:54 ` [PATCH v16 8/8] Documentation/cxl: Document DPA partition layout and ordering rules Anisa Su
` (2 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Anisa Su @ 2026-10-10 22:54 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
From: Ira Weiny <iweiny@kernel.org>
Device partitions share one flat DPA space in a fixed order: static
volatile capacity at DPA 0, static persistent capacity immediately above
it, and dynamic capacity above all static capacity. The static pair is
mandated by CXL r4.0 8.2.10.9.2.1 "Get Partition Info", Table 8-310: the
device "shall provide this volatile capacity starting at DPA 0" and
"shall provide this persistent capacity starting at the DPA immediately
following the volatile capacity". Dynamic capacity has no such rule.
Table 8-347 only requires the region base to be 256M aligned, so placing
it directly above static capacity is a Linux requirement,
enforced by cxl_configure_dcd().
DPA 0 end
+---------------+---------------+---------------------------+
| ram | pmem | dynamic_ram_1 |
+---------------+---------------+---------------------------+
part[0] part[1] part[2]
Signed-off-by: Ira Weiny <iweiny@kernel.org>
Co-developed-by: Anisa Su <anisa.su@samsung.com>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Tested-by: Wonjae Lee <wj28.lee@samsung.com>
Tested-by: Junhee Park <jh9934.park@samsung.com>
Tested-by: Heesoo Kim <habil.kim@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
---
drivers/cxl/core/hdm.c | 10 ++++++++++
drivers/cxl/core/memdev.c | 32 +++++++++-----------------------
drivers/cxl/cxlmem.h | 12 ------------
drivers/cxl/mem.c | 2 +-
include/cxl/cxl.h | 20 ++++++++++++++++++++
5 files changed, 40 insertions(+), 36 deletions(-)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 379540246333..ec5742debb52 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -470,6 +470,16 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
return 0;
}
+ /* Verify partitions are in expected order. */
+ for (int i = 1; i < info->nr_partitions; i++) {
+ if (info->part[i].mode < info->part[i - 1].mode) {
+ dev_err(dev, "Partition order mismatch: %d (%s) follows %d (%s)\n",
+ i, cxl_mode_name(info->part[i].mode),
+ i - 1, cxl_mode_name(info->part[i - 1].mode));
+ return -EINVAL;
+ }
+ }
+
cxlds->dpa_res = DEFINE_RES_MEM(0, info->size);
for (int i = 0; i < info->nr_partitions; i++) {
diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
index 71493231f5e5..787988e92965 100644
--- a/drivers/cxl/core/memdev.c
+++ b/drivers/cxl/core/memdev.c
@@ -77,20 +77,12 @@ static ssize_t label_storage_size_show(struct device *dev,
}
static DEVICE_ATTR_RO(label_storage_size);
-static resource_size_t cxl_ram_size(struct cxl_dev_state *cxlds)
-{
- /* Static RAM is only expected at partition 0. */
- if (cxlds->part[0].mode != CXL_PARTMODE_RAM)
- return 0;
- return resource_size(&cxlds->part[0].res);
-}
-
static ssize_t ram_size_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
struct cxl_dev_state *cxlds = cxlmd->cxlds;
- unsigned long long len = cxl_ram_size(cxlds);
+ unsigned long long len = cxl_part_size(cxlds, CXL_PARTMODE_RAM);
return sysfs_emit(buf, "%#llx\n", len);
}
@@ -103,7 +95,7 @@ static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr,
{
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
struct cxl_dev_state *cxlds = cxlmd->cxlds;
- unsigned long long len = cxl_pmem_size(cxlds);
+ unsigned long long len = cxl_part_size(cxlds, CXL_PARTMODE_PMEM);
return sysfs_emit(buf, "%#llx\n", len);
}
@@ -426,10 +418,11 @@ static struct attribute *cxl_memdev_attributes[] = {
NULL,
};
-static struct cxl_dpa_perf *to_pmem_perf(struct cxl_dev_state *cxlds)
+static struct cxl_dpa_perf *part_perf(struct cxl_dev_state *cxlds,
+ enum cxl_partition_mode mode)
{
for (int i = 0; i < cxlds->nr_partitions; i++)
- if (cxlds->part[i].mode == CXL_PARTMODE_PMEM)
+ if (cxlds->part[i].mode == mode)
return &cxlds->part[i].perf;
return NULL;
}
@@ -440,7 +433,7 @@ static ssize_t pmem_qos_class_show(struct device *dev,
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
struct cxl_dev_state *cxlds = cxlmd->cxlds;
- return sysfs_emit(buf, "%d\n", to_pmem_perf(cxlds)->qos_class);
+ return sysfs_emit(buf, "%d\n", part_perf(cxlds, CXL_PARTMODE_PMEM)->qos_class);
}
static struct device_attribute dev_attr_pmem_qos_class =
@@ -452,20 +445,13 @@ static struct attribute *cxl_memdev_pmem_attributes[] = {
NULL,
};
-static struct cxl_dpa_perf *to_ram_perf(struct cxl_dev_state *cxlds)
-{
- if (cxlds->part[0].mode != CXL_PARTMODE_RAM)
- return NULL;
- return &cxlds->part[0].perf;
-}
-
static ssize_t ram_qos_class_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
struct cxl_dev_state *cxlds = cxlmd->cxlds;
- return sysfs_emit(buf, "%d\n", to_ram_perf(cxlds)->qos_class);
+ return sysfs_emit(buf, "%d\n", part_perf(cxlds, CXL_PARTMODE_RAM)->qos_class);
}
static struct device_attribute dev_attr_ram_qos_class =
@@ -501,7 +487,7 @@ static umode_t cxl_ram_visible(struct kobject *kobj, struct attribute *a, int n)
{
struct device *dev = kobj_to_dev(kobj);
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
- struct cxl_dpa_perf *perf = to_ram_perf(cxlmd->cxlds);
+ struct cxl_dpa_perf *perf = part_perf(cxlmd->cxlds, CXL_PARTMODE_RAM);
if (a == &dev_attr_ram_qos_class.attr &&
(!perf || perf->qos_class == CXL_QOS_CLASS_INVALID))
@@ -520,7 +506,7 @@ static umode_t cxl_pmem_visible(struct kobject *kobj, struct attribute *a, int n
{
struct device *dev = kobj_to_dev(kobj);
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
- struct cxl_dpa_perf *perf = to_pmem_perf(cxlmd->cxlds);
+ struct cxl_dpa_perf *perf = part_perf(cxlmd->cxlds, CXL_PARTMODE_PMEM);
if (a == &dev_attr_pmem_qos_class.attr &&
(!perf || perf->qos_class == CXL_QOS_CLASS_INVALID))
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index bac7e1ac715f..35268d1c387c 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -412,18 +412,6 @@ struct cxl_security_state {
#define CXL_MAX_DC_PARTITIONS 8
-static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
-{
- /*
- * Static PMEM may be at partition index 0 when there is no static RAM
- * capacity.
- */
- for (int i = 0; i < cxlds->nr_partitions; i++)
- if (cxlds->part[i].mode == CXL_PARTMODE_PMEM)
- return resource_size(&cxlds->part[i].res);
- return 0;
-}
-
static inline resource_size_t cxl_part_size(struct cxl_dev_state *cxlds,
enum cxl_partition_mode mode)
{
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 798e5c369cfc..9c4ef401cbad 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -139,7 +139,7 @@ static int cxl_mem_probe(struct device *dev)
return -ENXIO;
}
- if (cxl_pmem_size(cxlds) && IS_ENABLED(CONFIG_CXL_PMEM)) {
+ if (cxl_part_size(cxlds, CXL_PARTMODE_PMEM) && IS_ENABLED(CONFIG_CXL_PMEM)) {
rc = devm_cxl_add_nvdimm(dev, parent_port, cxlmd);
if (rc) {
if (rc == -ENODEV)
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index 728decda57fd..1c04a7823f64 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -130,6 +130,26 @@ struct cxl_dpa_perf {
int qos_class;
};
+/*
+ * Partitions share one flat DPA space in a fixed order:
+ *
+ * DPA 0 end
+ * +---------------+---------------+---------------------------+
+ * | ram | pmem | dynamic_ram_1 |
+ * +---------------+---------------+---------------------------+
+ * part[0] part[1] part[2]
+ *
+ * The static ram and pmem partition order is mandated by CXL r4.0
+ * 8.2.10.9.2.1 "Get Partition Info" (opcode 4100h), Table 8-310: volatile
+ * capacity starts at DPA 0 and persistent capacity starts at the DPA
+ * immediately following it. A dynamic partition has no such
+ * requirement -- 8.2.10.9.9.1 "Get Dynamic Capacity Configuration"
+ * (opcode 4800h), Table 8-347, only requires the DC Region Base to be
+ * 256MB aligned -- but Linux follows that precedent and requires it to
+ * start at the DPA immediately following static capacity: after pmem,
+ * after ram on a device with no pmem, or at DPA 0 on a device with no
+ * static capacity at all. cxl_configure_dcd() enforces it.
+ */
enum cxl_partition_mode {
CXL_PARTMODE_RAM,
CXL_PARTMODE_PMEM,
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v16 8/8] Documentation/cxl: Document DPA partition layout and ordering rules
2026-10-10 22:54 [PATCH v16 0/8] DCD Prep Series Anisa Su
` (6 preceding siblings ...)
2026-10-10 22:54 ` [PATCH v16 7/8] cxl/core: Enforce partition order/simplify partition calls Anisa Su
@ 2026-10-10 22:54 ` Anisa Su
2026-10-12 13:34 ` Gregory Price
2026-10-12 14:24 ` [PATCH v16 0/8] DCD Prep Series Jonathan Cameron
2026-10-13 16:18 ` Dave Jiang
9 siblings, 1 reply; 17+ messages in thread
From: Anisa Su @ 2026-10-10 22:54 UTC (permalink / raw)
To: linux-cxl
Cc: nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Gregory Price, Richard Cheng,
Anisa Su
DC Partitions complicate DPA ordering. Add a DPA Partitions section to
cxl-driver.rst describing spec-mandated and Linux requirements for the
layout.
maturity-map.rst breaks the DCD entry into sub-items so the map shows
what this series lands: partition enumeration is [1], event handling
and DC-backed DAX regions remain [0] until the follow-on series enables
them. The parent stays [0]; nothing is usable yet.
Suggested-by: Gregory Price <gourry@gourry.net>
Signed-off-by: Anisa Su <anisa.su@samsung.com>
Tested-by: Wonjae Lee <wj28.lee@samsung.com>
Tested-by: Junhee Park <jh9934.park@samsung.com>
Tested-by: Heesoo Kim <habil.kim@samsung.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
---
.../driver-api/cxl/linux/cxl-driver.rst | 35 +++++++++++++++++++
Documentation/driver-api/cxl/maturity-map.rst | 4 +++
2 files changed, 39 insertions(+)
diff --git a/Documentation/driver-api/cxl/linux/cxl-driver.rst b/Documentation/driver-api/cxl/linux/cxl-driver.rst
index dd6dd17dc536..212df4fb8d63 100644
--- a/Documentation/driver-api/cxl/linux/cxl-driver.rst
+++ b/Documentation/driver-api/cxl/linux/cxl-driver.rst
@@ -181,6 +181,41 @@ A Memory Device is a discrete base object that is not a port. While the
physical device it belongs to may also host an `endpoint`, the relationship
between an `endpoint` and a `memdev` is not captured in sysfs.
+DPA Partitions
+~~~~~~~~~~~~~~
+A memory device presents its capacity as one flat `Device Physical Address`
+(DPA) space divided into `partitions`, which Linux lays out in a fixed
+order::
+
+ DPA 0 end
+ +---------------+---------------+---------------------------+
+ | ram | pmem | dynamic_ram_1 |
+ +---------------+---------------+---------------------------+
+ part[0] part[1] part[2]
+
+Part of that order is required by the CXL specification and part of it is a
+Linux choice.
+
+The `ram` and `pmem` order is mandated. CXL r4.0 section 8.2.10.9.2.1 "Get
+Partition Info" (4100h), Table 8-310, mandates that volatile capacity starts
+at DPA 0 and pmem starts at the DPA immediately following it.
+
+Dynamic Capacity partitions only need to be 256MB aligned according to
+CXL r4.0 section 8.2.10.9.9.1 "Get Dynamic Capacity Configuration"
+(opcode 4800h), Table 8-347. So a device could leave a gap between ram/pmem
+(static) capacity and its first DC partition, or between one DC partition
+and the next.
+
+Linux chooses not to support gaps between static and dynamic capacity: the
+first DC partition must begin at the DPA immediately following static
+capacity -- after pmem, after ram on a device with no pmem, or at DPA 0 on
+a device with no static capacity at all.
+
+Currently, only one dynamic partition is supported. A device may report up
+to eight (CXL r4.0 Table 8-346); Linux configures the first as its
+`dynamic_ram_1` partition. Gaps between DC partitions are not checked, since
+only the first is used.
+
Port Relationships
~~~~~~~~~~~~~~~~~~
In our example described above, there are four host bridges attached to the
diff --git a/Documentation/driver-api/cxl/maturity-map.rst b/Documentation/driver-api/cxl/maturity-map.rst
index 282c1102dd81..fefd31899229 100644
--- a/Documentation/driver-api/cxl/maturity-map.rst
+++ b/Documentation/driver-api/cxl/maturity-map.rst
@@ -150,6 +150,10 @@ Memory-pooling
* [1] Hotplug of LDs (via PCI hotplug)
* [0] Dynamic Capacity Device (DCD) Support
+ * [1] DC partition enumeration / configuration (Get DC Config, CDAT DSMAS, event interrupts)
+ * [0] Extent add / release event handling
+ * [0] DC-backed DAX regions
+
Multi-host sharing
------------------
--
2.43.0
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v16 8/8] Documentation/cxl: Document DPA partition layout and ordering rules
2026-10-10 22:54 ` [PATCH v16 8/8] Documentation/cxl: Document DPA partition layout and ordering rules Anisa Su
@ 2026-10-12 13:34 ` Gregory Price
0 siblings, 0 replies; 17+ messages in thread
From: Gregory Price @ 2026-10-12 13:34 UTC (permalink / raw)
To: Anisa Su
Cc: linux-cxl, nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Jonathan Cameron, Davidlohr Bueso, Ira Weiny, Vishal Verma,
Fan Ni, Li Ming, Benjamin Cheatham, Richard Cheng, Anisa Su
On Sun, Oct 11, 2026 at 07:54:59AM +0900, Anisa Su wrote:
> DC Partitions complicate DPA ordering. Add a DPA Partitions section to
> cxl-driver.rst describing spec-mandated and Linux requirements for the
> layout.
>
> maturity-map.rst breaks the DCD entry into sub-items so the map shows
> what this series lands: partition enumeration is [1], event handling
> and DC-backed DAX regions remain [0] until the follow-on series enables
> them. The parent stays [0]; nothing is usable yet.
>
> Suggested-by: Gregory Price <gourry@gourry.net>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
> Tested-by: Wonjae Lee <wj28.lee@samsung.com>
> Tested-by: Junhee Park <jh9934.park@samsung.com>
> Tested-by: Heesoo Kim <habil.kim@samsung.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Gregory Price (Meta) <gourry@gourry.net>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v16 0/8] DCD Prep Series
2026-10-10 22:54 [PATCH v16 0/8] DCD Prep Series Anisa Su
` (7 preceding siblings ...)
2026-10-10 22:54 ` [PATCH v16 8/8] Documentation/cxl: Document DPA partition layout and ordering rules Anisa Su
@ 2026-10-12 14:24 ` Jonathan Cameron
2026-10-13 16:18 ` Dave Jiang
9 siblings, 0 replies; 17+ messages in thread
From: Jonathan Cameron @ 2026-10-12 14:24 UTC (permalink / raw)
To: Anisa Su
Cc: linux-cxl, nvdimm, linux-kernel, Dave Jiang, Alison Schofield,
Davidlohr Bueso, Ira Weiny, Vishal Verma, Fan Ni, Li Ming,
Benjamin Cheatham, Gregory Price, Richard Cheng, Anisa Su
On Sun, 11 Oct 2026 07:54:51 +0900
Anisa Su <anisa.su887@gmail.com> wrote:
> These are the first eight patches of the Dynamic Capacity Device (DCD)
> series. They set up: DCD enumeration, CDAT handling for DC partitions,
> the event interrupt plumbing, a preparatory refactor, and
> documentation of the DPA partition layout. They stand alone and keep DCD
> disabled. They are not dependent on the rest of the series.
> Patch 1 detects the 48h command set and then leaves mds->dcd_supported
> false. The flag is only turned on by the series that adds DCD event
> handling, so every DCD specific path added here is shut off at runtime:
> cxl_configure_dcd() never runs, no DC partition is created, no DCD
> interrupt is armed, and the CXL_PARTMODE_DYNAMIC_RAM paths are
> unreachable. The intent is to land the enumeration and plumbing while
> the extent to DAX pipeline is still under review.
>
> Based on v7.3-rc6
> v15: https://lore.kernel.org/linux-cxl/20261007201828.952-1-anisa.su@samsung.com/
Hi Anisa,
For me, only that tiny reordering of the __free(kfree) and related pointer declaration
needs fixing before this merges. As I mentioned in that patch, maybe Dave
would be willing to tweak that - obviously that also depends on what responses
you get from others!
Thanks,
Jonathan
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v16 0/8] DCD Prep Series
2026-10-10 22:54 [PATCH v16 0/8] DCD Prep Series Anisa Su
` (8 preceding siblings ...)
2026-10-12 14:24 ` [PATCH v16 0/8] DCD Prep Series Jonathan Cameron
@ 2026-10-13 16:18 ` Dave Jiang
9 siblings, 0 replies; 17+ messages in thread
From: Dave Jiang @ 2026-10-13 16:18 UTC (permalink / raw)
To: Anisa Su, linux-cxl
Cc: nvdimm, linux-kernel, Alison Schofield, Jonathan Cameron,
Davidlohr Bueso, Ira Weiny, Vishal Verma, Fan Ni, Li Ming,
Benjamin Cheatham, Gregory Price, Richard Cheng, Anisa Su
On 10/10/26 3:54 PM, Anisa Su wrote:
> These are the first eight patches of the Dynamic Capacity Device (DCD)
> series. They set up: DCD enumeration, CDAT handling for DC partitions,
> the event interrupt plumbing, a preparatory refactor, and
> documentation of the DPA partition layout. They stand alone and keep DCD
> disabled. They are not dependent on the rest of the series.
> Patch 1 detects the 48h command set and then leaves mds->dcd_supported
> false. The flag is only turned on by the series that adds DCD event
> handling, so every DCD specific path added here is shut off at runtime:
> cxl_configure_dcd() never runs, no DC partition is created, no DCD
> interrupt is armed, and the CXL_PARTMODE_DYNAMIC_RAM paths are
> unreachable. The intent is to land the enumeration and plumbing while
> the extent to DAX pipeline is still under review.
>
> Based on v7.3-rc6
> v15: https://lore.kernel.org/linux-cxl/20261007201828.952-1-anisa.su@samsung.com/
>
> v15 -> v16 Changes:
> ===================
> A quick respin:
>
> - Patch 2: cxl_configure_dcd() took Identify Total Capacity as the end
> of static capacity, but Total Capacity is only required to be >=
> ram + pmem. The static end now comes from the last static partition's end dpa
> +1 instead of info->size. Check that DC starts from there. (Richard).
>
> - Patch 3: dsmas_entry.qos_class initialized as CXL_QOS_CLASS_INVALID, so a
> DSMAS entry that is skipped for lack of DSLBIS, or whose QTG lookup
> fails, no longer reaches update_perf_entry() with qos_class 0, which
> is a valid class. (Sashiko).
>
> The DSMAD handle check now checks handle > U8_MAX instead of
> handle & ~0xFF (Dave).
>
> - Patch 6: when the DCD vector cannot be requested, tell the device
> not to use the vector: dcd_settings is cleared with
> Set Event Interrupt Policy, so a device does not keep signalling a
> vector with no handler while the
> host considers DCD off. The Set command is re-factored into a new helper
> cxl_event_set_int_policy() (Richard).
>
> All other patches are unchanged.
> I kept the review tags on patch 3, since the changes are minimal and
> dropped tags from 2 and 6.
>
> Patch organization
> ==================
> 1-3: enumerate DCD command support, read the DC configuration, and pick
> up DSMAS data for DC partitions.
> 4-6: split event msgnum configuration from irq setup, factor out the
> interrupt policy check, then configure the DCD event interrupt.
> 7: preparatory refactor -- enforce partition order while collapsing
> the ram/pmem specific partition helpers into one.
> 8: document the DPA partition layout the previous patches enforce,
> and where Linux is stricter than the specification.
>
> Testing
> =======
> This series leaves mds->dcd_supported false on purpose, so
> cxl_configure_dcd(), cxl_dev_dc_identify() and cxl_dc_check() are
> unreachable at runtime as posted. The tests below are done with the rest
> of the series on top, otherwise testing would not yield any meaningful
> results.
>
> HW:
> Tested add and release of one 2G tagged extent on a DCD with a sharable
> partition, driven from the system's BMC with FM-API Initiate Dynamic
> Capacity Add / Release over MCTP, to confirm the DCD interrupt
> configuration and the DSMAS attributes are read properly. The device
> is sharable, so an add without a tag and sequence number is refused.
>
>
> cxl_test:
> ndctl cxl test suite
> 16 of 17 pass, cxl-features.sh skips for lack of FWCTL
>
> Anisa Su (1):
> Documentation/cxl: Document DPA partition layout and ordering rules
>
> Ira Weiny (7):
> cxl/mbox: Flag support for Dynamic Capacity Devices (DCD)
> cxl/mem: Read dynamic capacity configuration from the device
> cxl/cdat: Gather DSMAS data for DCD partitions
> cxl/events: Split event msgnum configuration from irq setup
> cxl/pci: Factor out interrupt policy check
> cxl/mem: Configure dynamic capacity interrupts
> cxl/core: Enforce partition order/simplify partition calls
>
> .../driver-api/cxl/linux/cxl-driver.rst | 35 +++
> Documentation/driver-api/cxl/maturity-map.rst | 4 +
> drivers/cxl/core/cdat.c | 99 +++++-
> drivers/cxl/core/hdm.c | 24 +-
> drivers/cxl/core/mbox.c | 285 ++++++++++++++++++
> drivers/cxl/core/memdev.c | 100 ++++--
> drivers/cxl/cxl.h | 14 +-
> drivers/cxl/cxlmem.h | 88 +++++-
> drivers/cxl/mem.c | 2 +-
> drivers/cxl/pci.c | 207 ++++++++++---
> include/cxl/cxl.h | 29 +-
> tools/testing/cxl/test/mem.c | 2 +-
> 12 files changed, 792 insertions(+), 97 deletions(-)
>
>
> base-commit: a90ee4305c4a5df72c11b31dacfdc76e00fcf78a
Applied to cxl/next
e4478834aa09
c801107605f3
9c45dd3684a5
726ac97330a4
f9c672229ca8
a7d2b5e9c4f5
b5d93fa1b7ac
13797539ae78
^ permalink raw reply [flat|nested] 17+ messages in thread