From: George Neacsu via B4 Relay <devnull+geocausa.gmail.com@kernel.org>
To: Bryan O'Donoghue <bod@kernel.org>, Vinod Koul <vkoul@kernel.org>,
David Heidelberg <david@ixit.cz>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Loic Poulain <loic.poulain@oss.qualcomm.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>,
Vikram Sharma <vikram.sharma@oss.qualcomm.com>,
Suresh Vankadara <svankada@qti.qualcomm.com>,
tjose@qti.qualcomm.com,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Manivannan Sadhasivam <mani@kernel.org>,
linux-phy@lists.infradead.org, linux-media@vger.kernel.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
George Neacsu <geocausa@gmail.com>
Subject: [PATCH v3 1/6] phy: Add MIPI C-PHY mode and configuration options
Date: Fri, 16 Oct 2026 15:56:11 +0100 [thread overview]
Message-ID: <20261016-x1e-cphy-rfc-v3-1-40a346a72153@gmail.com> (raw)
In-Reply-To: <20261016-x1e-cphy-rfc-v3-0-40a346a72153@gmail.com>
From: George Neacsu <geocausa@gmail.com>
The generic PHY framework has a mode and configuration options for MIPI
D-PHY but none for C-PHY, so a CSI-2 receiver has no way to ask a PHY
that does both for C-PHY. Add PHY_MODE_MIPI_CPHY and struct
phy_configure_opts_mipi_cphy. The options are the two values a receiver
knows: the symbol rate on each trio and the number of trios.
The first user is the Qualcomm CSI2 PHY, whose X1E80100 instances carry
the C-PHY front camera of the Surface Pro 11.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: George Neacsu <geocausa@gmail.com>
---
include/linux/phy/phy-mipi-cphy.h | 29 +++++++++++++++++++++++++++++
include/linux/phy/phy.h | 5 +++++
2 files changed, 34 insertions(+)
diff --git a/include/linux/phy/phy-mipi-cphy.h b/include/linux/phy/phy-mipi-cphy.h
new file mode 100644
index 0000000000..9b748d577b
--- /dev/null
+++ b/include/linux/phy/phy-mipi-cphy.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __PHY_MIPI_CPHY_H_
+#define __PHY_MIPI_CPHY_H_
+
+#include <linux/types.h>
+
+/**
+ * struct phy_configure_opts_mipi_cphy - MIPI C-PHY configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * MIPI C-PHY phy.
+ */
+struct phy_configure_opts_mipi_cphy {
+ /**
+ * @symbol_rate:
+ *
+ * Symbol rate on each trio, in symbols per second.
+ */
+ u64 symbol_rate;
+
+ /**
+ * @trios:
+ *
+ * Number of active trios.
+ */
+ u8 trios;
+};
+
+#endif /* __PHY_MIPI_CPHY_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index c480d6cb42..f123378340 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -19,6 +19,7 @@
#include <linux/phy/phy-dp.h>
#include <linux/phy/phy-hdmi.h>
#include <linux/phy/phy-lvds.h>
+#include <linux/phy/phy-mipi-cphy.h>
#include <linux/phy/phy-mipi-dphy.h>
#include <linux/phy/phy-thunderbolt.h>
@@ -42,6 +43,7 @@ enum phy_mode {
PHY_MODE_PCIE,
PHY_MODE_ETHERNET,
PHY_MODE_MIPI_DPHY,
+ PHY_MODE_MIPI_CPHY,
PHY_MODE_SATA,
PHY_MODE_LVDS,
PHY_MODE_DP,
@@ -69,6 +71,8 @@ union phy_notify {
*
* @mipi_dphy: Configuration set applicable for phys supporting
* the MIPI_DPHY phy mode.
+ * @mipi_cphy: Configuration set applicable for phys supporting
+ * the MIPI_CPHY phy mode.
* @dp: Configuration set applicable for phys supporting
* the DisplayPort protocol.
* @lvds: Configuration set applicable for phys supporting
@@ -78,6 +82,7 @@ union phy_notify {
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
+ struct phy_configure_opts_mipi_cphy mipi_cphy;
struct phy_configure_opts_dp dp;
struct phy_configure_opts_lvds lvds;
struct phy_configure_opts_hdmi hdmi;
--
2.53.0
next prev parent reply other threads:[~2026-10-16 14:56 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 14:56 [PATCH v3 0/6] phy: qcom-mipi-csi2: C-PHY for X1E80100 George Neacsu via B4 Relay
2026-10-16 14:56 ` George Neacsu via B4 Relay [this message]
2026-10-16 14:56 ` [PATCH v3 2/6] phy: Add MIPI C-PHY configuration helpers George Neacsu via B4 Relay
2026-10-16 14:56 ` [PATCH v3 3/6] phy: qcom-mipi-csi2: Rename the D-PHY init sequence George Neacsu via B4 Relay
2026-10-16 14:56 ` [PATCH v3 4/6] phy: qcom-mipi-csi2: Add lane mask and lane polarity helpers George Neacsu via B4 Relay
2026-10-16 14:56 ` [PATCH v3 5/6] phy: qcom-mipi-csi2: Use fsleep() for init sequence delays George Neacsu via B4 Relay
2026-10-16 14:56 ` [PATCH v3 6/6] phy: qcom-mipi-csi2: Add C-PHY support for X1E80100 George Neacsu via B4 Relay
2026-10-16 15:10 ` David Heidelberg
2026-10-16 16:08 ` George Neacsu
2026-10-16 16:09 ` [PATCH v3 0/6] phy: qcom-mipi-csi2: C-PHY " Bryan O'Donoghue
2026-10-16 21:48 ` George Neacsu
2026-10-16 22:04 ` David Heidelberg
2026-10-17 4:31 ` Anusha Arun Nandi
2026-10-17 7:04 ` George Neacsu
2026-10-17 13:35 ` Bryan O'Donoghue
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