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From: George Neacsu via B4 Relay <devnull+geocausa.gmail.com@kernel.org>
To: Bryan O'Donoghue <bod@kernel.org>, Vinod Koul <vkoul@kernel.org>,
	 David Heidelberg <david@ixit.cz>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
	 Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
	 Loic Poulain <loic.poulain@oss.qualcomm.com>,
	 Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	 Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>,
	 Vikram Sharma <vikram.sharma@oss.qualcomm.com>,
	 Suresh Vankadara <svankada@qti.qualcomm.com>,
	tjose@qti.qualcomm.com,
	 Mauro Carvalho Chehab <mchehab@kernel.org>,
	 Manivannan Sadhasivam <mani@kernel.org>,
	linux-phy@lists.infradead.org,  linux-media@vger.kernel.org,
	linux-arm-msm@vger.kernel.org,  linux-kernel@vger.kernel.org,
	Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
	 George Neacsu <geocausa@gmail.com>
Subject: [PATCH v3 3/6] phy: qcom-mipi-csi2: Rename the D-PHY init sequence
Date: Fri, 16 Oct 2026 15:56:13 +0100	[thread overview]
Message-ID: <20261016-x1e-cphy-rfc-v3-3-40a346a72153@gmail.com> (raw)
In-Reply-To: <20261016-x1e-cphy-rfc-v3-0-40a346a72153@gmail.com>

From: George Neacsu <geocausa@gmail.com>

The init sequence and its size describe the D-PHY mode only. Call them
dphy_init_seq and dphy_lane_array_size, so that a C-PHY sequence can sit
next to them under matching names.

No functional change.

Suggested-by: Bryan O'Donoghue <bod@kernel.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: George Neacsu <geocausa@gmail.com>
---
 drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 8 ++++----
 drivers/phy/qualcomm/phy-qcom-mipi-csi2.h          | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
index 966d79c98f..b2d4ec3e81 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
@@ -246,8 +246,8 @@ phy_qcom_mipi_csi2_gen2_config_lanes(struct mipi_csi2phy_device *csi2phy,
 				     u8 settle_cnt)
 {
 	const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy);
-	const struct mipi_csi2phy_lane_regs *r = regs->init_seq;
-	int i, array_size = regs->lane_array_size;
+	const struct mipi_csi2phy_lane_regs *r = regs->dphy_init_seq;
+	int i, array_size = regs->dphy_lane_array_size;
 	u32 val;
 
 	for (i = 0; i < array_size; i++, r++) {
@@ -372,8 +372,8 @@ static struct mipi_csi2_genpd x1e_genpds[] = {
 const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = {
 	.ops = &phy_qcom_mipi_csi2_ops_3ph_1_0,
 	.reg_info = {
-		.init_seq = lane_regs_x1e80100,
-		.lane_array_size = ARRAY_SIZE(lane_regs_x1e80100),
+		.dphy_init_seq = lane_regs_x1e80100,
+		.dphy_lane_array_size = ARRAY_SIZE(lane_regs_x1e80100),
 		.common_regs_offset = 0x1000,
 	},
 	.supply_names = (const char **)x1e_supplies,
diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h
index 7e55ae0073..0d6031a4d8 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h
@@ -48,8 +48,8 @@ struct mipi_csi2phy_lane_regs {
 };
 
 struct mipi_csi2phy_device_regs {
-	const struct mipi_csi2phy_lane_regs *init_seq;
-	const int lane_array_size;
+	const struct mipi_csi2phy_lane_regs *dphy_init_seq;
+	const int dphy_lane_array_size;
 	const u32 common_regs_offset;
 };
 

-- 
2.53.0



  parent reply	other threads:[~2026-10-16 14:56 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-16 14:56 [PATCH v3 0/6] phy: qcom-mipi-csi2: C-PHY for X1E80100 George Neacsu via B4 Relay
2026-10-16 14:56 ` [PATCH v3 1/6] phy: Add MIPI C-PHY mode and configuration options George Neacsu via B4 Relay
2026-10-16 14:56 ` [PATCH v3 2/6] phy: Add MIPI C-PHY configuration helpers George Neacsu via B4 Relay
2026-10-16 14:56 ` George Neacsu via B4 Relay [this message]
2026-10-16 14:56 ` [PATCH v3 4/6] phy: qcom-mipi-csi2: Add lane mask and lane polarity helpers George Neacsu via B4 Relay
2026-10-16 14:56 ` [PATCH v3 5/6] phy: qcom-mipi-csi2: Use fsleep() for init sequence delays George Neacsu via B4 Relay
2026-10-16 14:56 ` [PATCH v3 6/6] phy: qcom-mipi-csi2: Add C-PHY support for X1E80100 George Neacsu via B4 Relay
2026-10-16 15:10   ` David Heidelberg
2026-10-16 16:08     ` George Neacsu
2026-10-16 16:09 ` [PATCH v3 0/6] phy: qcom-mipi-csi2: C-PHY " Bryan O'Donoghue
2026-10-16 21:48   ` George Neacsu
2026-10-16 22:04     ` David Heidelberg
2026-10-17  4:31 ` Anusha Arun Nandi
2026-10-17  7:04   ` George Neacsu
2026-10-17 13:35     ` Bryan O'Donoghue

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