* [PATCH] reset: spacemit: Fix the RCPU2 PWM reset registers
@ 2026-10-17 14:08 Hung-Chun Tseng
2026-10-18 0:00 ` Yixun Lan
0 siblings, 1 reply; 2+ messages in thread
From: Hung-Chun Tseng @ 2026-10-17 14:08 UTC (permalink / raw)
To: Philipp Zabel, Guodong Xu, Yixun Lan
Cc: Troy Mitchell, Alex Elder, linux-riscv, spacemit, linux-kernel
Every entry in k1_rcpu2_resets[] uses RCPU2_PWM9_CLK_RST, so asserting
or deasserting the reset of any RCPU2 PWM from 0 to 8 acts on PWM9
instead. Each PWM has its own register, RCPU2_PWMn_CLK_RST at offset
4 * n, as k1-syscon.h already defines.
On a Milk-V Jupiter running the vendor kernel, which uses RCPU2 PWM2
for the fan, the RCPU2 registers read:
0x00: 0x4 0x04: 0x4 0x08: 0x1 0x0c: 0x4 ... 0x24: 0x4
Only PWM2's register has its reset deasserted, which matches one
register per PWM.
Use the matching register for each reset. No in-tree device tree uses
the RCPU2 PWMs yet, so this has no effect on current boards, but it
would break the first one that does.
Build-tested only (riscv defconfig, W=1); the fix could not be tested
at runtime, as mainline has no RCPU2 PWM node to exercise it.
Fixes: c479d7cf06c3 ("reset: spacemit: add support for SpacemiT CCU resets")
Assisted-by: claude-opus-5-5
Signed-off-by: Hung-Chun Tseng <alan.tseng.cs@gmail.com>
---
drivers/reset/spacemit/reset-spacemit-k1.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/reset/spacemit/reset-spacemit-k1.c b/drivers/reset/spacemit/reset-spacemit-k1.c
index 8f3b5329e..dbd783c13 100644
--- a/drivers/reset/spacemit/reset-spacemit-k1.c
+++ b/drivers/reset/spacemit/reset-spacemit-k1.c
@@ -154,15 +154,15 @@ static const struct ccu_reset_controller_data k1_rcpu_reset_data = {
};
static const struct ccu_reset_data k1_rcpu2_resets[] = {
- [RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
- [RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
- [RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
- [RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
- [RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
- [RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
- [RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
- [RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
- [RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
+ [RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM0_CLK_RST, BIT(2), BIT(0)),
+ [RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM1_CLK_RST, BIT(2), BIT(0)),
+ [RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM2_CLK_RST, BIT(2), BIT(0)),
+ [RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM3_CLK_RST, BIT(2), BIT(0)),
+ [RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM4_CLK_RST, BIT(2), BIT(0)),
+ [RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM5_CLK_RST, BIT(2), BIT(0)),
+ [RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM6_CLK_RST, BIT(2), BIT(0)),
+ [RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM7_CLK_RST, BIT(2), BIT(0)),
+ [RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM8_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM9] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
};
--
2.43.0
^ permalink raw reply [flat|nested] 2+ messages in thread* Re: [PATCH] reset: spacemit: Fix the RCPU2 PWM reset registers
2026-10-17 14:08 [PATCH] reset: spacemit: Fix the RCPU2 PWM reset registers Hung-Chun Tseng
@ 2026-10-18 0:00 ` Yixun Lan
0 siblings, 0 replies; 2+ messages in thread
From: Yixun Lan @ 2026-10-18 0:00 UTC (permalink / raw)
To: Hung-Chun Tseng
Cc: Philipp Zabel, Guodong Xu, Troy Mitchell, Alex Elder,
linux-riscv, spacemit, linux-kernel
Hi Hung-Chun,
On 22:08 Sat 17 Oct , Hung-Chun Tseng wrote:
> Every entry in k1_rcpu2_resets[] uses RCPU2_PWM9_CLK_RST, so asserting
> or deasserting the reset of any RCPU2 PWM from 0 to 8 acts on PWM9
> instead. Each PWM has its own register, RCPU2_PWMn_CLK_RST at offset
> 4 * n, as k1-syscon.h already defines.
>
> On a Milk-V Jupiter running the vendor kernel, which uses RCPU2 PWM2
> for the fan, the RCPU2 registers read:
>
> 0x00: 0x4 0x04: 0x4 0x08: 0x1 0x0c: 0x4 ... 0x24: 0x4
>
> Only PWM2's register has its reset deasserted, which matches one
> register per PWM.
>
Also match vendor's code, see
https://gitee.com/spacemit-buildroot/linux-6.6/blob/k1-bl-v2.2.y/drivers/reset/reset-spacemit-k1x.c#L317
> Use the matching register for each reset. No in-tree device tree uses
> the RCPU2 PWMs yet, so this has no effect on current boards, but it
> would break the first one that does.
>
> Build-tested only (riscv defconfig, W=1); the fix could not be tested
> at runtime, as mainline has no RCPU2 PWM node to exercise it.
>
> Fixes: c479d7cf06c3 ("reset: spacemit: add support for SpacemiT CCU resets")
> Assisted-by: claude-opus-5-5
> Signed-off-by: Hung-Chun Tseng <alan.tseng.cs@gmail.com>
> ---
> drivers/reset/spacemit/reset-spacemit-k1.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
Reviewed-by: Yixun Lan <dlan@kernel.org>
> diff --git a/drivers/reset/spacemit/reset-spacemit-k1.c b/drivers/reset/spacemit/reset-spacemit-k1.c
> index 8f3b5329e..dbd783c13 100644
> --- a/drivers/reset/spacemit/reset-spacemit-k1.c
> +++ b/drivers/reset/spacemit/reset-spacemit-k1.c
> @@ -154,15 +154,15 @@ static const struct ccu_reset_controller_data k1_rcpu_reset_data = {
> };
>
> static const struct ccu_reset_data k1_rcpu2_resets[] = {
> - [RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
> - [RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
> - [RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
> - [RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
> - [RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
> - [RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
> - [RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
> - [RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
> - [RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
> + [RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM0_CLK_RST, BIT(2), BIT(0)),
> + [RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM1_CLK_RST, BIT(2), BIT(0)),
> + [RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM2_CLK_RST, BIT(2), BIT(0)),
> + [RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM3_CLK_RST, BIT(2), BIT(0)),
> + [RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM4_CLK_RST, BIT(2), BIT(0)),
> + [RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM5_CLK_RST, BIT(2), BIT(0)),
> + [RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM6_CLK_RST, BIT(2), BIT(0)),
> + [RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM7_CLK_RST, BIT(2), BIT(0)),
> + [RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM8_CLK_RST, BIT(2), BIT(0)),
> [RESET_RCPU2_PWM9] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
> };
>
> --
> 2.43.0
>
--
Yixun Lan (dlan)
^ permalink raw reply [flat|nested] 2+ messages in thread
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2026-10-17 14:08 [PATCH] reset: spacemit: Fix the RCPU2 PWM reset registers Hung-Chun Tseng
2026-10-18 0:00 ` Yixun Lan
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