[PATCH 0/8] interconnect: qcom: implement support for MSM8998

[PATCH 0/8] interconnect: qcom: implement support for MSM8998

[Dmitry Baryshkov]

Add bindings, driver and DT bits necessary to enable bus scaling on
Qualcomm MSM8998.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Dmitry Baryshkov (3):
      dt-bindings: interconnect: add Qualcomm MSM8998 NoC
      arm64: dts: qcom: msm8998: add interconnect provider nodes
      arm64: dts: qcom: msm8998: wire up interconnect paths

Konrad Dybcio (5):
      soc: qcom: smd-rpm: Handle zero-length errors
      interconnect: qcom: icc-rpm: depopulate SMD RPM child NoCs
      interconnect: qcom: icc-rpm: skip duplicate SMD RPM node votes
      interconnect: qcom: icc-rpm: Allow negative QoS offset
      interconnect: qcom: add MSM8998 interconnect provider

 .../bindings/interconnect/qcom,msm8998.yaml        |  192 ++
 arch/arm64/boot/dts/qcom/msm8998.dtsi              |  127 ++
 drivers/interconnect/qcom/Kconfig                  |   11 +
 drivers/interconnect/qcom/Makefile                 |    2 +
 drivers/interconnect/qcom/icc-rpm.c                |    5 +-
 drivers/interconnect/qcom/icc-rpm.h                |    2 +-
 drivers/interconnect/qcom/msm8998.c                | 1978 ++++++++++++++++++++
 drivers/soc/qcom/smd-rpm.c                         |    6 +
 include/dt-bindings/interconnect/qcom,msm8998.h    |  133 ++
 9 files changed, 2453 insertions(+), 3 deletions(-)
---
base-commit: 2efb7a11f1aa4d2dc285fe2680cca22cb9f72f64
change-id: 20261019-msm8998-icc-8009da583105

Best regards,
--  
With best wishes
Dmitry

[PATCH 1/8] dt-bindings: interconnect: add Qualcomm MSM8998 NoC

[Dmitry Baryshkov]

The MSM8998 interconnect provider driver has no device tree schema, so
the provider nodes it binds to can neither be described nor validated.

Document the eight MSM8998 NoC devices.  Unlike the older RPM
interconnect bindings, the bus clocks of these providers are RPM
resources handled by the driver itself, so only the interface clocks
appear in the device tree.  The MMSS AHB NoC has no register range of
its own - it shares the register space of the MMSS NoC - and is
therefore described as a child of the latter.

Co-developed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 .../bindings/interconnect/qcom,msm8998.yaml        | 192 +++++++++++++++++++++
 include/dt-bindings/interconnect/qcom,msm8998.h    | 133 ++++++++++++++
 2 files changed, 325 insertions(+)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998.yaml
new file mode 100644
index 000000000000..0a05dc620cfd
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998.yaml
@@ -0,0 +1,192 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,msm8998.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm MSM8998 Network-On-Chip interconnect
+
+maintainers:
+  - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
+  - Konrad Dybcio <konradybcio@kernel.org>
+
+description: |
+  The Qualcomm MSM8998 interconnect providers support adjusting the
+  bandwidth requirements between the various NoC fabrics.
+
+properties:
+  compatible:
+    enum:
+      - qcom,msm8998-a1noc
+      - qcom,msm8998-a2noc
+      - qcom,msm8998-bimc
+      - qcom,msm8998-cnoc
+      - qcom,msm8998-gnoc
+      - qcom,msm8998-mnoc
+      - qcom,msm8998-mnoc-ahb
+      - qcom,msm8998-snoc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 4
+
+  clock-names:
+    minItems: 1
+    maxItems: 4
+
+required:
+  - compatible
+
+unevaluatedProperties: false
+
+allOf:
+  - $ref: qcom,rpm-common.yaml#
+  - if:
+      properties:
+        compatible:
+          const: qcom,msm8998-a1noc
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Aggregate1 NoC UFS AXI Clock
+            - description: UFS AXI Clock
+            - description: Aggregate1 NoC USB3 AXI Clock
+            - description: BLSP2 AHB Clock
+
+        clock-names:
+          items:
+            - const: aggre1_ufs_axi
+            - const: ufs_axi
+            - const: usb_axi
+            - const: blsp2_ahb
+
+  - if:
+      properties:
+        compatible:
+          const: qcom,msm8998-a2noc
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: SDCC2 AHB Clock
+            - description: SDCC4 AHB Clock
+            - description: BLSP1 AHB Clock
+            - description: IPA Clock
+
+        clock-names:
+          items:
+            - const: sdcc2_ahb
+            - const: sdcc4_ahb
+            - const: blsp1_ahb
+            - const: ipa
+
+  - if:
+      properties:
+        compatible:
+          enum:
+            - qcom,msm8998-cnoc
+            - qcom,msm8998-snoc
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: CPU-NoC High-performance Bus Clock
+
+        clock-names:
+          const: iface
+
+  - if:
+      properties:
+        compatible:
+          const: qcom,msm8998-mnoc
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: CPU-NoC High-performance Bus Clock
+            - description: MMSS NoC AXI Clock
+
+        clock-names:
+          items:
+            - const: iface
+            - const: mnoc_bus
+
+        interconnect-mnoc-ahb:
+          type: object
+          additionalProperties: true
+
+          properties:
+            compatible:
+              const: qcom,msm8998-mnoc-ahb
+
+  - if:
+      properties:
+        compatible:
+          const: qcom,msm8998-mnoc-ahb
+
+    then:
+      description:
+        The MMSS AHB NoC shares its register space with the MMSS NoC, so it is
+        described as a child of the latter and has no register range of its own.
+
+      properties:
+        clocks:
+          items:
+            - description: MMSS AHB Clock
+
+        clock-names:
+          const: bus
+
+      required:
+        - clocks
+        - clock-names
+
+    else:
+      required:
+        - reg
+
+  - if:
+      properties:
+        compatible:
+          enum:
+            - qcom,msm8998-bimc
+            - qcom,msm8998-gnoc
+
+    then:
+      properties:
+        clocks: false
+        clock-names: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-msm8998.h>
+    #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
+
+    interconnect@1008300 {
+        compatible = "qcom,msm8998-bimc";
+        reg = <0x01008300 0x77d00>;
+        #interconnect-cells = <2>;
+    };
+
+    interconnect@1740000 {
+        compatible = "qcom,msm8998-mnoc";
+        reg = <0x01740000 0x10000>;
+        clocks = <&mmcc MNOC_AHB_CLK>, <&mmcc MNOC_MAXI_CLK>;
+        clock-names = "iface", "mnoc_bus";
+        #interconnect-cells = <2>;
+
+        interconnect-mnoc-ahb {
+            compatible = "qcom,msm8998-mnoc-ahb";
+            clocks = <&mmcc AHB_CLK_SRC>;
+            clock-names = "bus";
+            #interconnect-cells = <2>;
+        };
+    };
diff --git a/include/dt-bindings/interconnect/qcom,msm8998.h b/include/dt-bindings/interconnect/qcom,msm8998.h
new file mode 100644
index 000000000000..3eb571e65554
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,msm8998.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8998_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8998_H
+
+/* A1NOC */
+#define MASTER_PCIE_0			0
+#define MASTER_USB3			1
+#define MASTER_UFS			2
+#define MASTER_BLSP_2			3
+#define SLAVE_A1NOC_SNOC		4
+
+/* A2NOC */
+#define MASTER_IPA			0
+#define MASTER_CNOC_A2NOC		1
+#define MASTER_SDCC_2			2
+#define MASTER_SDCC_4			3
+#define MASTER_TSIF			4
+#define MASTER_BLSP_1			5
+#define MASTER_CRVIRT_A2NOC		6
+#define MASTER_CRYPTO_C0		7
+#define SLAVE_A2NOC_SNOC		8
+#define SLAVE_CRVIRT_A2NOC		9
+
+/* BIMC */
+#define MASTER_GNOC_BIMC		0
+#define MASTER_OXILI			1
+#define MASTER_MNOC_BIMC		2
+#define MASTER_SNOC_BIMC		3
+#define SLAVE_EBI			4
+#define SLAVE_HMSS_L3			5
+#define SLAVE_BIMC_SNOC_0		6
+#define SLAVE_BIMC_SNOC_1		7
+
+/* CNOC */
+#define MASTER_SNOC_CNOC		0
+#define MASTER_QDSS_DAP			1
+#define SLAVE_CNOC_A2NOC		2
+#define SLAVE_SSC_CFG			3
+#define SLAVE_MPM			4
+#define SLAVE_PMIC_ARB			5
+#define SLAVE_TLMM_NORTH		6
+#define SLAVE_PIMEM_CFG			7
+#define SLAVE_IMEM_CFG			8
+#define SLAVE_MESSAGE_RAM		9
+#define SLAVE_SKL			10
+#define SLAVE_BIMC_CFG			11
+#define SLAVE_PRNG			12
+#define SLAVE_A2NOC_CFG			13
+#define SLAVE_IPA			14
+#define SLAVE_TCSR			15
+#define SLAVE_SNOC_CFG			16
+#define SLAVE_CLK_CTL			17
+#define SLAVE_GLM			18
+#define SLAVE_SPDM			19
+#define SLAVE_GPUSS_CFG			20
+#define SLAVE_CNOC_MNOC_CFG		21
+#define SLAVE_QM_CFG			22
+#define SLAVE_MSS_CFG			23
+#define SLAVE_UFS_CFG			24
+#define SLAVE_TLMM_WEST			25
+#define SLAVE_A1NOC_CFG			26
+#define SLAVE_AHB2PHY			27
+#define SLAVE_BLSP_2			28
+#define SLAVE_PDM			29
+#define SLAVE_USB3_0			30
+#define SLAVE_A1NOC_SMMU_CFG		31
+#define SLAVE_BLSP_1			32
+#define SLAVE_SDCC_2			33
+#define SLAVE_SDCC_4			34
+#define SLAVE_TSIF			35
+#define SLAVE_QDSS_CFG			36
+#define SLAVE_TLMM_EAST			37
+#define SLAVE_CNOC_MNOC_MMSS_CFG	38
+#define SLAVE_SRVC_CNOC			39
+
+/* GNOC */
+#define MASTER_APSS_PROC		0
+#define SLAVE_GNOC_BIMC			1
+
+/* MNOC */
+#define MASTER_CNOC_MNOC_CFG		0
+#define MASTER_CPP			1
+#define MASTER_JPEG			2
+#define MASTER_MDP_P0			3
+#define MASTER_MDP_P1			4
+#define MASTER_ROTATOR			5
+#define MASTER_VENUS			6
+#define MASTER_VFE			7
+#define MASTER_VENUS_VMEM		8
+#define SLAVE_MNOC_BIMC			9
+#define SLAVE_VMEM			10
+#define SLAVE_SRVC_MNOC			11
+
+/* MNOC_AHB */
+#define MASTER_CNOC_MNOC_MMSS_CFG	0
+#define SLAVE_CAMERA_CFG		1
+#define SLAVE_CAMERA_THROTTLE_CFG	2
+#define SLAVE_MISC_CFG			3
+#define SLAVE_VENUS_THROTTLE_CFG	4
+#define SLAVE_VENUS_CFG			5
+#define SLAVE_VMEM_CFG			6
+#define SLAVE_MMSS_CLK_XPU_CFG		7
+#define SLAVE_MMSS_CLK_CFG		8
+#define SLAVE_DISPLAY_CFG		9
+#define SLAVE_DISPLAY_THROTTLE_CFG	10
+#define SLAVE_SMMU_CFG			11
+
+/* SNOC */
+#define MASTER_HMSS			0
+#define MASTER_QDSS_BAM			1
+#define MASTER_SNOC_CFG			2
+#define MASTER_BIMC_SNOC_0		3
+#define MASTER_BIMC_SNOC_1		4
+#define MASTER_A1NOC_SNOC		5
+#define MASTER_A2NOC_SNOC		6
+#define MASTER_QDSS_ETR			7
+#define SLAVE_HMSS			8
+#define SLAVE_LPASS			9
+#define SLAVE_WLAN			10
+#define SLAVE_SNOC_BIMC			11
+#define SLAVE_SNOC_CNOC			12
+#define SLAVE_IMEM			13
+#define SLAVE_PIMEM			14
+#define SLAVE_QDSS_STM			15
+#define SLAVE_PCIE_0			16
+#define SLAVE_SRVC_SNOC			17
+
+#endif

-- 
2.47.3

[PATCH 2/8] soc: qcom: smd-rpm: Handle zero-length errors

[Dmitry Baryshkov]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Prevent a potential underflow as the code below uses 'ALIGN(n, 4) - 1'
as an index into an array. For n=0, that ends up as '-1U'.

Fixes: 936f14cf4e67 ("soc: qcom: Driver for the Qualcomm RPM over SMD")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
[db: report the empty error as -EINVAL instead of a success]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/soc/qcom/smd-rpm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c
index f2b3e02abdf1..3677c645edfa 100644
--- a/drivers/soc/qcom/smd-rpm.c
+++ b/drivers/soc/qcom/smd-rpm.c
@@ -173,6 +173,12 @@ static int qcom_smd_rpm_callback(struct rpmsg_device *rpdev,
 		case RPM_MSG_TYPE_MSG_ID:
 			break;
 		case RPM_MSG_TYPE_ERR:
+			if (!msg_length) {
+				dev_err(&rpdev->dev, "Got unknown RPM error\n");
+				status = -EINVAL;
+				break;
+			}
+
 			len = min_t(u32, ALIGN(msg_length, 4), sizeof(msgbuf));
 			memcpy_fromio(msgbuf, msg->message, len);
 			msgbuf[len - 1] = 0;

-- 
2.47.3

[PATCH 3/8] interconnect: qcom: icc-rpm: depopulate SMD RPM child NoCs

[Dmitry Baryshkov]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

qnoc_probe() creates the child NoC devices (the QCM2290 and SM6115
virtual NoCs, the MSM8939 SNoC MM and the MSM8998 MMSS AHB NoC) with
of_platform_populate(), but nothing ever removes them. Unbinding the
parent NoC therefore leaves the children bound, although they live in
the parent's register space and use the parent's regmap, which devres
frees together with the parent. Binding the parent again does not
recreate them either, as their DT nodes are still marked as populated,
so they keep running with the state of the previous parent instance.

Populate the children with devm_of_platform_populate() and depopulate
them at the start of qnoc_remove(), so that they go away before the
provider they depend on. Leaving it to devres alone would only remove
them after qnoc_remove() has already torn the parent provider down.

Fixes: e39bf2972c6e ("interconnect: icc-rpm: Support child NoC device probe")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/interconnect/qcom/icc-rpm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c
index 6f325789a96e..ddc7df31ed33 100644
--- a/drivers/interconnect/qcom/icc-rpm.c
+++ b/drivers/interconnect/qcom/icc-rpm.c
@@ -677,7 +677,7 @@ int qnoc_probe(struct platform_device *pdev)
 
 	/* Populate child NoC devices if any */
 	if (of_get_child_count(dev->of_node) > 0) {
-		ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
+		ret = devm_of_platform_populate(dev);
 		if (ret)
 			goto err_deregister_provider;
 	}
@@ -699,6 +699,7 @@ void qnoc_remove(struct platform_device *pdev)
 {
 	struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
 
+	devm_of_platform_depopulate(&pdev->dev);
 	icc_provider_deregister(&qp->provider);
 	icc_nodes_remove(&qp->provider);
 	clk_disable_unprepare(qp->bus_clk);

-- 
2.47.3

[PATCH 4/8] interconnect: qcom: icc-rpm: skip duplicate SMD RPM node votes

[Dmitry Baryshkov]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

icc_sync_state() can invoke the provider set callback with the same
node as both source and destination. Do not submit a second RPM
bandwidth vote for that node.

Fixes: 751f4d14cdb4 ("interconnect: icc-rpm: Set destination bandwidth as well as source bandwidth")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/interconnect/qcom/icc-rpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c
index ddc7df31ed33..6e8e0bcf79bf 100644
--- a/drivers/interconnect/qcom/icc-rpm.c
+++ b/drivers/interconnect/qcom/icc-rpm.c
@@ -427,7 +427,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 	if (ret)
 		return ret;
 
-	if (dst_qn) {
+	if (dst_qn && dst != src) {
 		ret = qcom_icc_rpm_set(dst_qn, dst_qn->sum_avg, qp->ignore_enxio);
 		if (ret)
 			return ret;

-- 
2.47.3

[PATCH 5/8] interconnect: qcom: icc-rpm: Allow negative QoS offset

[Dmitry Baryshkov]

From: Konrad Dybcio <konrad.dybcio@linaro.org>

In some very very very very unfortunate cases, the correct offset of
the QoS registers will be.. negative. One such case is MSM8998, where
The DDR BWMON occupies what-would-be-the-BIMC-base which we usually
take into account with the register calculation, making the actual
BIMC node start at what-would-be-the-BIMC-base+0x300.

In order to keep the calculation code sane, the simplest - however
ugly it may be - solution is to allow the offset to be negative.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/interconnect/qcom/icc-rpm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
index d2c5f45eeedf..d0ffc042e926 100644
--- a/drivers/interconnect/qcom/icc-rpm.h
+++ b/drivers/interconnect/qcom/icc-rpm.h
@@ -57,7 +57,7 @@ struct qcom_icc_provider {
 	struct icc_provider provider;
 	enum qcom_icc_type type;
 	struct regmap *regmap;
-	unsigned int qos_offset;
+	int qos_offset;
 	u16 ab_coeff;
 	u16 ib_coeff;
 	u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM];

-- 
2.47.3

[PATCH 6/8] interconnect: qcom: add MSM8998 interconnect provider

[Dmitry Baryshkov]

From: Konrad Dybcio <konrad.dybcio@linaro.org>

Add the complete MSM8998 SMD RPM interconnect topology, including all NoC
providers, global graph IDs, local onecell binding IDs, QoS configuration,
and RPM clock resources.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/interconnect/qcom/Kconfig   |   11 +
 drivers/interconnect/qcom/Makefile  |    2 +
 drivers/interconnect/qcom/msm8998.c | 1978 +++++++++++++++++++++++++++++++++++
 3 files changed, 1991 insertions(+)

diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index 7f3a977e8f10..1287f525085d 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -158,6 +158,17 @@ config INTERCONNECT_QCOM_MSM8996
 	  This is a driver for the Qualcomm Network-on-Chip on msm8996-based
 	  platforms.
 
+config INTERCONNECT_QCOM_MSM8998
+	tristate "Qualcomm MSM8998 interconnect driver"
+	depends on INTERCONNECT_QCOM
+	depends on QCOM_SMD_RPM
+	depends on ARM64 || COMPILE_TEST
+	select INTERCONNECT_QCOM_SMD_RPM
+	default ARCH_QCOM
+	help
+	  This is a driver for the Qualcomm Network-on-Chip on msm8998-based
+	  platforms.
+
 config INTERCONNECT_QCOM_NORD
 	tristate "Qualcomm Nord interconnect driver"
 	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index a71478aaf591..078598ee782f 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -19,6 +19,7 @@ qnoc-msm8953-objs			:= msm8953.o
 qnoc-msm8974-objs			:= msm8974.o
 qnoc-msm8976-objs			:= msm8976.o
 qnoc-msm8996-objs			:= msm8996.o
+qnoc-msm8998-objs			:= msm8998.o
 qnoc-nord-objs				:= nord.o
 icc-osm-l3-objs				:= osm-l3.o
 qnoc-qcm2290-objs			:= qcm2290.o
@@ -69,6 +70,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8953) += qnoc-msm8953.o
 obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o
 obj-$(CONFIG_INTERCONNECT_QCOM_MSM8976) += qnoc-msm8976.o
 obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o
+obj-$(CONFIG_INTERCONNECT_QCOM_MSM8998) += qnoc-msm8998.o
 obj-$(CONFIG_INTERCONNECT_QCOM_NORD) += qnoc-nord.o
 obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
 obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o
diff --git a/drivers/interconnect/qcom/msm8998.c b/drivers/interconnect/qcom/msm8998.c
new file mode 100644
index 000000000000..df0f5f206d46
--- /dev/null
+++ b/drivers/interconnect/qcom/msm8998.c
@@ -0,0 +1,1978 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Qualcomm MSM8998 Network-on-Chip (NoC) QoS driver
+ * Copyright (c) 2020, AngeloGioacchino Del Regno
+ *                     <angelogioacchino.delregno@somainline.org>
+ * Copyright (C) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
+ * Copyright (c) 2023, Linaro Limited
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interconnect/qcom,msm8998.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/interconnect-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "icc-rpm.h"
+
+static const char * const a1noc_intf_clocks[] = {
+	"aggre1_ufs_axi",
+	"ufs_axi",
+	"usb_axi",
+	"blsp2_ahb",
+};
+
+static const char * const a2noc_intf_clocks[] = {
+	"sdcc2_ahb",
+	"sdcc4_ahb",
+	"blsp1_ahb",
+	"ipa", /* mas_ipa */
+};
+
+static const char * const mnoc_intf_clocks[] = {
+	"iface",
+	"mnoc_bus",
+};
+
+static const char * const cnoc_snoc_intf_clocks[] = {
+	"iface",
+};
+
+enum {
+	MSM8998_MASTER_IPA,
+	MSM8998_MASTER_CNOC_A2NOC,
+	MSM8998_MASTER_SDCC_2,
+	MSM8998_MASTER_SDCC_4,
+	MSM8998_MASTER_BLSP_1,
+	MSM8998_MASTER_BLSP_2,
+	MSM8998_MASTER_UFS,
+	MSM8998_MASTER_USB_HS,
+	MSM8998_MASTER_USB3,
+	MSM8998_MASTER_CRYPTO_C0,
+	MSM8998_MASTER_GNOC_BIMC,
+	MSM8998_MASTER_OXILI,
+	MSM8998_MASTER_MNOC_BIMC,
+	MSM8998_MASTER_SNOC_BIMC,
+	MSM8998_MASTER_PIMEM,
+	MSM8998_MASTER_SNOC_CNOC,
+	MSM8998_MASTER_QDSS_DAP,
+	MSM8998_MASTER_APPS_PROC,
+	MSM8998_MASTER_CNOC_MNOC_MMSS_CFG,
+	MSM8998_MASTER_CNOC_MNOC_CFG,
+	MSM8998_MASTER_CPP,
+	MSM8998_MASTER_JPEG,
+	MSM8998_MASTER_MDP_P0,
+	MSM8998_MASTER_MDP_P1,
+	MSM8998_MASTER_VENUS,
+	MSM8998_MASTER_VFE,
+	MSM8998_MASTER_QDSS_ETR,
+	MSM8998_MASTER_QDSS_BAM,
+	MSM8998_MASTER_SNOC_CFG,
+	MSM8998_MASTER_BIMC_SNOC,
+	MSM8998_MASTER_A1NOC_SNOC,
+	MSM8998_MASTER_A2NOC_SNOC,
+	MSM8998_MASTER_GNOC_SNOC,
+	MSM8998_MASTER_PCIE_0,
+	MSM8998_MASTER_A2NOC_TSIF,
+	MSM8998_MASTER_CRVIRT_A2NOC,
+	MSM8998_MASTER_ROTATOR,
+	MSM8998_MASTER_VENUS_VMEM,
+	MSM8998_MASTER_HMSS,
+	MSM8998_MASTER_BIMC_SNOC_0,
+	MSM8998_MASTER_BIMC_SNOC_1,
+
+	MSM8998_SLAVE_A1NOC_SNOC,
+	MSM8998_SLAVE_A2NOC_SNOC,
+	MSM8998_SLAVE_EBI,
+	MSM8998_SLAVE_HMSS_L3,
+	MSM8998_SLAVE_CNOC_A2NOC,
+	MSM8998_SLAVE_MPM,
+	MSM8998_SLAVE_PMIC_ARB,
+	MSM8998_SLAVE_TLMM_NORTH,
+	MSM8998_SLAVE_TCSR,
+	MSM8998_SLAVE_PIMEM_CFG,
+	MSM8998_SLAVE_IMEM_CFG,
+	MSM8998_SLAVE_MESSAGE_RAM,
+	MSM8998_SLAVE_GLM,
+	MSM8998_SLAVE_BIMC_CFG,
+	MSM8998_SLAVE_PRNG,
+	MSM8998_SLAVE_SPDM,
+	MSM8998_SLAVE_QDSS_CFG,
+	MSM8998_SLAVE_CNOC_MNOC_CFG,
+	MSM8998_SLAVE_SNOC_CFG,
+	MSM8998_SLAVE_QM_CFG,
+	MSM8998_SLAVE_CLK_CTL,
+	MSM8998_SLAVE_MSS_CFG,
+	MSM8998_SLAVE_UFS_CFG,
+	MSM8998_SLAVE_A2NOC_CFG,
+	MSM8998_SLAVE_A2NOC_SMMU_CFG,
+	MSM8998_SLAVE_GPUSS_CFG,
+	MSM8998_SLAVE_AHB2PHY,
+	MSM8998_SLAVE_BLSP_1,
+	MSM8998_SLAVE_SDCC_2,
+	MSM8998_SLAVE_SDCC_4,
+	MSM8998_SLAVE_BLSP_2,
+	MSM8998_SLAVE_PDM,
+	MSM8998_SLAVE_CNOC_MNOC_MMSS_CFG,
+	MSM8998_SLAVE_USB_HS,
+	MSM8998_SLAVE_USB3_0,
+	MSM8998_SLAVE_SRVC_CNOC,
+	MSM8998_SLAVE_GNOC_BIMC,
+	MSM8998_SLAVE_GNOC_SNOC,
+	MSM8998_SLAVE_CAMERA_CFG,
+	MSM8998_SLAVE_CAMERA_THROTTLE_CFG,
+	MSM8998_SLAVE_MISC_CFG,
+	MSM8998_SLAVE_VENUS_THROTTLE_CFG,
+	MSM8998_SLAVE_VENUS_CFG,
+	MSM8998_SLAVE_MMSS_CLK_XPU_CFG,
+	MSM8998_SLAVE_MMSS_CLK_CFG,
+	MSM8998_SLAVE_MNOC_MPU_CFG,
+	MSM8998_SLAVE_DISPLAY_CFG,
+	MSM8998_SLAVE_CSI_PHY_CFG,
+	MSM8998_SLAVE_DISPLAY_THROTTLE_CFG,
+	MSM8998_SLAVE_SMMU_CFG,
+	MSM8998_SLAVE_MNOC_BIMC,
+	MSM8998_SLAVE_SRVC_MNOC,
+	MSM8998_SLAVE_HMSS,
+	MSM8998_SLAVE_LPASS,
+	MSM8998_SLAVE_WLAN,
+	MSM8998_SLAVE_CDSP,
+	MSM8998_SLAVE_IPA,
+	MSM8998_SLAVE_SNOC_BIMC,
+	MSM8998_SLAVE_SNOC_CNOC,
+	MSM8998_SLAVE_IMEM,
+	MSM8998_SLAVE_PIMEM,
+	MSM8998_SLAVE_QDSS_STM,
+	MSM8998_SLAVE_SRVC_SNOC,
+	MSM8998_SLAVE_BIMC_SNOC_0,
+	MSM8998_SLAVE_BIMC_SNOC_1,
+	MSM8998_SLAVE_SSC_CFG,
+	MSM8998_SLAVE_SKL,
+	MSM8998_SLAVE_TLMM_WEST,
+	MSM8998_SLAVE_A1NOC_CFG,
+	MSM8998_SLAVE_A1NOC_SMMU_CFG,
+	MSM8998_SLAVE_TSIF,
+	MSM8998_SLAVE_TLMM_EAST,
+	MSM8998_SLAVE_CRVIRT_A2NOC,
+	MSM8998_SLAVE_VMEM_CFG,
+	MSM8998_SLAVE_VMEM,
+	MSM8998_SLAVE_PCIE_0,
+};
+
+static const u16 master_pcie_0_links[] = {
+	MSM8998_SLAVE_A1NOC_SNOC,
+};
+
+static struct qcom_icc_node mas_pcie_0 = {
+	.name = "master_pcie_0",
+	.id = MSM8998_MASTER_PCIE_0,
+	.buswidth = 16,
+	.mas_rpm_id = 65,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_FIXED,
+	.qos.areq_prio = 1,
+	.qos.prio_level = 1,
+	.qos.qos_port = 1,
+	.links = master_pcie_0_links,
+	.num_links = ARRAY_SIZE(master_pcie_0_links),
+};
+
+static const u16 master_usb3_links[] = {
+	MSM8998_SLAVE_A1NOC_SNOC,
+};
+
+static struct qcom_icc_node mas_usb3 = {
+	.name = "master_usb3",
+	.id = MSM8998_MASTER_USB3,
+	.buswidth = 16,
+	.mas_rpm_id = 32,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_FIXED,
+	.qos.areq_prio = 1,
+	.qos.prio_level = 1,
+	.qos.qos_port = 2,
+	.links = master_usb3_links,
+	.num_links = ARRAY_SIZE(master_usb3_links),
+};
+
+static const u16 master_ufs_links[] = {
+	MSM8998_SLAVE_A1NOC_SNOC,
+};
+
+static struct qcom_icc_node mas_ufs = {
+	.name = "master_ufs",
+	.id = MSM8998_MASTER_UFS,
+	.buswidth = 16,
+	.mas_rpm_id = 68,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_FIXED,
+	.qos.areq_prio = 1,
+	.qos.prio_level = 1,
+	.qos.qos_port = 0,
+	.links = master_ufs_links,
+	.num_links = ARRAY_SIZE(master_ufs_links),
+};
+
+static const u16 master_blsp_2_links[] = {
+	MSM8998_SLAVE_A1NOC_SNOC,
+};
+
+static struct qcom_icc_node mas_blsp_2 = {
+	.name = "master_blsp_2",
+	.id = MSM8998_MASTER_BLSP_2,
+	.buswidth = 16,
+	.mas_rpm_id = 39,
+	.slv_rpm_id = -1,
+	.links = master_blsp_2_links,
+	.num_links = ARRAY_SIZE(master_blsp_2_links),
+};
+
+static const u16 master_cnoc_a2noc_links[] = {
+	MSM8998_SLAVE_A2NOC_SNOC,
+};
+
+static struct qcom_icc_node mas_cnoc_a2noc = {
+	.name = "master_cnoc_a2noc",
+	.id = MSM8998_MASTER_CNOC_A2NOC,
+	.buswidth = 8,
+	.mas_rpm_id = 146,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = master_cnoc_a2noc_links,
+	.num_links = ARRAY_SIZE(master_cnoc_a2noc_links),
+};
+
+static const u16 master_ipa_links[] = {
+	MSM8998_SLAVE_A2NOC_SNOC,
+};
+
+static struct qcom_icc_node mas_ipa = {
+	.name = "master_ipa",
+	.id = MSM8998_MASTER_IPA,
+	.buswidth = 8,
+	.mas_rpm_id = 59,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_FIXED,
+	.qos.areq_prio = 1,
+	.qos.prio_level = 1,
+	.qos.qos_port = 1,
+	.links = master_ipa_links,
+	.num_links = ARRAY_SIZE(master_ipa_links),
+};
+
+static const u16 master_sdcc_2_links[] = {
+	MSM8998_SLAVE_A2NOC_SNOC,
+};
+
+static struct qcom_icc_node mas_sdcc_2 = {
+	.name = "master_sdcc_2",
+	.id = MSM8998_MASTER_SDCC_2,
+	.buswidth = 8,
+	.mas_rpm_id = 35,
+	.slv_rpm_id = -1,
+	.links = master_sdcc_2_links,
+	.num_links = ARRAY_SIZE(master_sdcc_2_links),
+};
+
+static const u16 master_sdcc_4_links[] = {
+	MSM8998_SLAVE_A2NOC_SNOC,
+};
+
+static struct qcom_icc_node mas_sdcc_4 = {
+	.name = "master_sdcc_4",
+	.id = MSM8998_MASTER_SDCC_4,
+	.buswidth = 8,
+	.mas_rpm_id = 36,
+	.slv_rpm_id = -1,
+	.links = master_sdcc_4_links,
+	.num_links = ARRAY_SIZE(master_sdcc_4_links),
+};
+
+static const u16 master_a2noc_tsif_links[] = {
+	MSM8998_SLAVE_A2NOC_SNOC,
+};
+
+static struct qcom_icc_node mas_tsif = {
+	.name = "master_a2noc_tsif",
+	.id = MSM8998_MASTER_A2NOC_TSIF,
+	.buswidth = 4,
+	.mas_rpm_id = 37,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = master_a2noc_tsif_links,
+	.num_links = ARRAY_SIZE(master_a2noc_tsif_links),
+};
+
+static const u16 master_blsp_1_links[] = {
+	MSM8998_SLAVE_A2NOC_SNOC,
+};
+
+static struct qcom_icc_node mas_blsp_1 = {
+	.name = "master_blsp_1",
+	.id = MSM8998_MASTER_BLSP_1,
+	.buswidth = 16,
+	.mas_rpm_id = 41,
+	.slv_rpm_id = -1,
+	.links = master_blsp_1_links,
+	.num_links = ARRAY_SIZE(master_blsp_1_links),
+};
+
+static const u16 master_crvirt_a2noc_links[] = {
+	MSM8998_SLAVE_A2NOC_SNOC,
+};
+
+static struct qcom_icc_node mas_crvirt_a2noc = {
+	.name = "master_crvirt_a2noc",
+	.id = MSM8998_MASTER_CRVIRT_A2NOC,
+	.buswidth = 8,
+	.mas_rpm_id = 145,
+	.slv_rpm_id = -1,
+	.links = master_crvirt_a2noc_links,
+	.num_links = ARRAY_SIZE(master_crvirt_a2noc_links),
+};
+
+static const u16 master_gnoc_bimc_links[] = {
+	MSM8998_SLAVE_EBI,
+	MSM8998_SLAVE_BIMC_SNOC_0,
+};
+
+static struct qcom_icc_node mas_gnoc_bimc = {
+	.name = "master_gnoc_bimc",
+	.id = MSM8998_MASTER_GNOC_BIMC,
+	.channels = 2,
+	.buswidth = 8,
+	.mas_rpm_id = 144,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_FIXED,
+	.qos.areq_prio = 0,
+	.qos.prio_level = 0,
+	.qos.qos_port = 0,
+	.links = master_gnoc_bimc_links,
+	.num_links = ARRAY_SIZE(master_gnoc_bimc_links),
+};
+
+static const u16 master_oxili_links[] = {
+	MSM8998_SLAVE_BIMC_SNOC_1,
+	MSM8998_SLAVE_HMSS_L3,
+	MSM8998_SLAVE_EBI,
+	MSM8998_SLAVE_BIMC_SNOC_0,
+};
+
+static struct qcom_icc_node mas_oxili = {
+	.name = "master_oxili",
+	.id = MSM8998_MASTER_OXILI,
+	.channels = 2,
+	.buswidth = 8,
+	.mas_rpm_id = 6,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
+	.qos.areq_prio = 0,
+	.qos.prio_level = 0,
+	.qos.qos_port = 1,
+	.links = master_oxili_links,
+	.num_links = ARRAY_SIZE(master_oxili_links),
+};
+
+static const u16 master_mnoc_bimc_links[] = {
+	MSM8998_SLAVE_BIMC_SNOC_1,
+	MSM8998_SLAVE_HMSS_L3,
+	MSM8998_SLAVE_EBI,
+	MSM8998_SLAVE_BIMC_SNOC_0,
+};
+
+static struct qcom_icc_node mas_mnoc_bimc = {
+	.name = "master_mnoc_bimc",
+	.id = MSM8998_MASTER_MNOC_BIMC,
+	.channels = 2,
+	.buswidth = 8,
+	.mas_rpm_id = 2,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
+	.qos.areq_prio = 0,
+	.qos.prio_level = 0,
+	.qos.qos_port = 2,
+	.links = master_mnoc_bimc_links,
+	.num_links = ARRAY_SIZE(master_mnoc_bimc_links),
+};
+
+static const u16 master_snoc_bimc_links[] = {
+	MSM8998_SLAVE_HMSS_L3,
+	MSM8998_SLAVE_EBI,
+};
+
+static struct qcom_icc_node mas_snoc_bimc = {
+	.name = "master_snoc_bimc",
+	.id = MSM8998_MASTER_SNOC_BIMC,
+	.channels = 2,
+	.buswidth = 8,
+	.mas_rpm_id = 3,
+	.slv_rpm_id = -1,
+	.links = master_snoc_bimc_links,
+	.num_links = ARRAY_SIZE(master_snoc_bimc_links),
+};
+
+static const u16 master_snoc_cnoc_links[] = {
+	MSM8998_SLAVE_SKL,
+	MSM8998_SLAVE_BLSP_2,
+	MSM8998_SLAVE_MESSAGE_RAM,
+	MSM8998_SLAVE_TLMM_WEST,
+	MSM8998_SLAVE_TSIF,
+	MSM8998_SLAVE_MPM,
+	MSM8998_SLAVE_BIMC_CFG,
+	MSM8998_SLAVE_TLMM_EAST,
+	MSM8998_SLAVE_SPDM,
+	MSM8998_SLAVE_PIMEM_CFG,
+	MSM8998_SLAVE_A1NOC_SMMU_CFG,
+	MSM8998_SLAVE_BLSP_1,
+	MSM8998_SLAVE_CLK_CTL,
+	MSM8998_SLAVE_PRNG,
+	MSM8998_SLAVE_USB3_0,
+	MSM8998_SLAVE_QDSS_CFG,
+	MSM8998_SLAVE_QM_CFG,
+	MSM8998_SLAVE_A2NOC_CFG,
+	MSM8998_SLAVE_PMIC_ARB,
+	MSM8998_SLAVE_UFS_CFG,
+	MSM8998_SLAVE_SRVC_CNOC,
+	MSM8998_SLAVE_AHB2PHY,
+	MSM8998_SLAVE_IPA,
+	MSM8998_SLAVE_GLM,
+	MSM8998_SLAVE_SNOC_CFG,
+	MSM8998_SLAVE_SSC_CFG,
+	MSM8998_SLAVE_SDCC_2,
+	MSM8998_SLAVE_SDCC_4,
+	MSM8998_SLAVE_PDM,
+	MSM8998_SLAVE_CNOC_MNOC_MMSS_CFG,
+	MSM8998_SLAVE_CNOC_MNOC_CFG,
+	MSM8998_SLAVE_MSS_CFG,
+	MSM8998_SLAVE_IMEM_CFG,
+	MSM8998_SLAVE_A1NOC_CFG,
+	MSM8998_SLAVE_GPUSS_CFG,
+	MSM8998_SLAVE_TCSR,
+	MSM8998_SLAVE_TLMM_NORTH,
+};
+
+static struct qcom_icc_node mas_snoc_cnoc = {
+	.name = "master_snoc_cnoc",
+	.id = MSM8998_MASTER_SNOC_CNOC,
+	.buswidth = 8,
+	.mas_rpm_id = 52,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = master_snoc_cnoc_links,
+	.num_links = ARRAY_SIZE(master_snoc_cnoc_links),
+};
+
+static const u16 master_qdss_dap_links[] = {
+	MSM8998_SLAVE_SKL,
+	MSM8998_SLAVE_BLSP_2,
+	MSM8998_SLAVE_MESSAGE_RAM,
+	MSM8998_SLAVE_TLMM_WEST,
+	MSM8998_SLAVE_TSIF,
+	MSM8998_SLAVE_MPM,
+	MSM8998_SLAVE_BIMC_CFG,
+	MSM8998_SLAVE_TLMM_EAST,
+	MSM8998_SLAVE_SPDM,
+	MSM8998_SLAVE_PIMEM_CFG,
+	MSM8998_SLAVE_A1NOC_SMMU_CFG,
+	MSM8998_SLAVE_BLSP_1,
+	MSM8998_SLAVE_CLK_CTL,
+	MSM8998_SLAVE_PRNG,
+	MSM8998_SLAVE_USB3_0,
+	MSM8998_SLAVE_QDSS_CFG,
+	MSM8998_SLAVE_QM_CFG,
+	MSM8998_SLAVE_A2NOC_CFG,
+	MSM8998_SLAVE_PMIC_ARB,
+	MSM8998_SLAVE_UFS_CFG,
+	MSM8998_SLAVE_SRVC_CNOC,
+	MSM8998_SLAVE_AHB2PHY,
+	MSM8998_SLAVE_IPA,
+	MSM8998_SLAVE_GLM,
+	MSM8998_SLAVE_SNOC_CFG,
+	MSM8998_SLAVE_SDCC_2,
+	MSM8998_SLAVE_SDCC_4,
+	MSM8998_SLAVE_PDM,
+	MSM8998_SLAVE_CNOC_MNOC_MMSS_CFG,
+	MSM8998_SLAVE_CNOC_MNOC_CFG,
+	MSM8998_SLAVE_MSS_CFG,
+	MSM8998_SLAVE_IMEM_CFG,
+	MSM8998_SLAVE_A1NOC_CFG,
+	MSM8998_SLAVE_GPUSS_CFG,
+	MSM8998_SLAVE_SSC_CFG,
+	MSM8998_SLAVE_TCSR,
+	MSM8998_SLAVE_TLMM_NORTH,
+	MSM8998_SLAVE_CNOC_A2NOC,
+};
+
+static struct qcom_icc_node mas_qdss_dap = {
+	.name = "master_qdss_dap",
+	.id = MSM8998_MASTER_QDSS_DAP,
+	.buswidth = 8,
+	.mas_rpm_id = 49,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = master_qdss_dap_links,
+	.num_links = ARRAY_SIZE(master_qdss_dap_links),
+};
+
+static const u16 master_crypto_c0_links[] = {
+	MSM8998_SLAVE_CRVIRT_A2NOC,
+};
+
+static struct qcom_icc_node mas_crypto = {
+	.name = "master_crypto_c0",
+	.id = MSM8998_MASTER_CRYPTO_C0,
+	.buswidth = 650,
+	.mas_rpm_id = 23,
+	.slv_rpm_id = -1,
+	.links = master_crypto_c0_links,
+	.num_links = ARRAY_SIZE(master_crypto_c0_links),
+};
+
+static const u16 master_apps_proc_links[] = {
+	MSM8998_SLAVE_GNOC_BIMC,
+};
+
+static struct qcom_icc_node mas_apss_proc = {
+	.name = "master_apps_proc",
+	.id = MSM8998_MASTER_APPS_PROC,
+	.buswidth = 32,
+	.mas_rpm_id = 0,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = master_apps_proc_links,
+	.num_links = ARRAY_SIZE(master_apps_proc_links),
+};
+
+static const u16 master_cnoc_mnoc_mmss_cfg_links[] = {
+	MSM8998_SLAVE_CAMERA_THROTTLE_CFG,
+	MSM8998_SLAVE_VENUS_CFG,
+	MSM8998_SLAVE_MISC_CFG,
+	MSM8998_SLAVE_CAMERA_CFG,
+	MSM8998_SLAVE_DISPLAY_THROTTLE_CFG,
+	MSM8998_SLAVE_VENUS_THROTTLE_CFG,
+	MSM8998_SLAVE_DISPLAY_CFG,
+	MSM8998_SLAVE_MMSS_CLK_CFG,
+	MSM8998_SLAVE_VMEM_CFG,
+	MSM8998_SLAVE_MMSS_CLK_XPU_CFG,
+	MSM8998_SLAVE_SMMU_CFG,
+};
+
+static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = {
+	.name = "master_cnoc_mnoc_mmss_cfg",
+	.id = MSM8998_MASTER_CNOC_MNOC_MMSS_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = 4,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = master_cnoc_mnoc_mmss_cfg_links,
+	.num_links = ARRAY_SIZE(master_cnoc_mnoc_mmss_cfg_links),
+};
+
+static const u16 master_cnoc_mnoc_cfg_links[] = {
+	MSM8998_SLAVE_SRVC_MNOC,
+};
+
+static struct qcom_icc_node mas_cnoc_mnoc_cfg = {
+	.name = "master_cnoc_mnoc_cfg",
+	.id = MSM8998_MASTER_CNOC_MNOC_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = 5,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = master_cnoc_mnoc_cfg_links,
+	.num_links = ARRAY_SIZE(master_cnoc_mnoc_cfg_links),
+};
+
+static const u16 master_cpp_links[] = {
+	MSM8998_SLAVE_MNOC_BIMC,
+};
+
+static struct qcom_icc_node mas_cpp = {
+	.name = "master_cpp",
+	.id = MSM8998_MASTER_CPP,
+	.buswidth = 32,
+	.mas_rpm_id = 115,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
+	.qos.areq_prio = 0,
+	.qos.prio_level = 0,
+	.qos.qos_port = 5,
+	.links = master_cpp_links,
+	.num_links = ARRAY_SIZE(master_cpp_links),
+};
+
+static const u16 master_jpeg_links[] = {
+	MSM8998_SLAVE_MNOC_BIMC,
+};
+
+static struct qcom_icc_node mas_jpeg = {
+	.name = "master_jpeg",
+	.id = MSM8998_MASTER_JPEG,
+	.buswidth = 32,
+	.mas_rpm_id = 7,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
+	.qos.areq_prio = 0,
+	.qos.prio_level = 0,
+	.qos.qos_port = 7,
+	.links = master_jpeg_links,
+	.num_links = ARRAY_SIZE(master_jpeg_links),
+};
+
+static const u16 master_mdp_p0_links[] = {
+	MSM8998_SLAVE_MNOC_BIMC,
+};
+
+static struct qcom_icc_node mas_mdp_p0 = {
+	.name = "master_mdp_p0",
+	.id = MSM8998_MASTER_MDP_P0,
+	.buswidth = 32,
+	.mas_rpm_id = 8,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
+	.qos.areq_prio = 0,
+	.qos.prio_level = 0,
+	.qos.qos_port = 1,
+	.links = master_mdp_p0_links,
+	.num_links = ARRAY_SIZE(master_mdp_p0_links),
+};
+
+static const u16 master_mdp_p1_links[] = {
+	MSM8998_SLAVE_MNOC_BIMC,
+};
+
+static struct qcom_icc_node mas_mdp_p1 = {
+	.name = "master_mdp_p1",
+	.id = MSM8998_MASTER_MDP_P1,
+	.buswidth = 32,
+	.mas_rpm_id = 61,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
+	.qos.areq_prio = 0,
+	.qos.prio_level = 0,
+	.qos.qos_port = 2,
+	.links = master_mdp_p1_links,
+	.num_links = ARRAY_SIZE(master_mdp_p1_links),
+};
+
+static const u16 master_rotator_links[] = {
+	MSM8998_SLAVE_MNOC_BIMC,
+};
+
+static struct qcom_icc_node mas_rotator = {
+	.name = "master_rotator",
+	.id = MSM8998_MASTER_ROTATOR,
+	.buswidth = 32,
+	.mas_rpm_id = 120,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
+	.qos.areq_prio = 0,
+	.qos.prio_level = 0,
+	.qos.qos_port = 0,
+	.links = master_rotator_links,
+	.num_links = ARRAY_SIZE(master_rotator_links),
+};
+
+static const u16 master_venus_links[] = {
+	MSM8998_SLAVE_MNOC_BIMC,
+};
+
+static struct qcom_icc_node mas_venus = {
+	.name = "master_venus",
+	.id = MSM8998_MASTER_VENUS,
+	.channels = 2,
+	.buswidth = 32,
+	.mas_rpm_id = 9,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
+	.qos.areq_prio = 0,
+	.qos.prio_level = 0,
+	.qos.qos_port = 3,
+	.qos.aux_qos_port = 4,
+	.links = master_venus_links,
+	.num_links = ARRAY_SIZE(master_venus_links),
+};
+
+static const u16 master_vfe_links[] = {
+	MSM8998_SLAVE_MNOC_BIMC,
+};
+
+static struct qcom_icc_node mas_vfe = {
+	.name = "master_vfe",
+	.id = MSM8998_MASTER_VFE,
+	.buswidth = 32,
+	.mas_rpm_id = 11,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_BYPASS,
+	.qos.areq_prio = 0,
+	.qos.prio_level = 0,
+	.qos.qos_port = 6,
+	.links = master_vfe_links,
+	.num_links = ARRAY_SIZE(master_vfe_links),
+};
+
+static const u16 master_venus_vmem_links[] = {
+	MSM8998_SLAVE_VMEM,
+};
+
+static struct qcom_icc_node mas_venus_vmem = {
+	.name = "master_venus_vmem",
+	.id = MSM8998_MASTER_VENUS_VMEM,
+	.buswidth = 32,
+	.mas_rpm_id = 121,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = master_venus_vmem_links,
+	.num_links = ARRAY_SIZE(master_venus_vmem_links),
+};
+
+static const u16 master_hmss_links[] = {
+	MSM8998_SLAVE_PIMEM,
+	MSM8998_SLAVE_IMEM,
+	MSM8998_SLAVE_SNOC_BIMC,
+};
+
+static struct qcom_icc_node mas_hmss = {
+	.name = "master_hmss",
+	.id = MSM8998_MASTER_HMSS,
+	.buswidth = 16,
+	.mas_rpm_id = 118,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_FIXED,
+	.qos.areq_prio = 1,
+	.qos.prio_level = 1,
+	.qos.qos_port = 3,
+	.links = master_hmss_links,
+	.num_links = ARRAY_SIZE(master_hmss_links),
+};
+
+static const u16 master_qdss_bam_links[] = {
+	MSM8998_SLAVE_IMEM,
+	MSM8998_SLAVE_PIMEM,
+	MSM8998_SLAVE_SNOC_CNOC,
+	MSM8998_SLAVE_SNOC_BIMC,
+};
+
+static struct qcom_icc_node mas_qdss_bam = {
+	.name = "master_qdss_bam",
+	.id = MSM8998_MASTER_QDSS_BAM,
+	.buswidth = 16,
+	.mas_rpm_id = 19,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_FIXED,
+	.qos.areq_prio = 1,
+	.qos.prio_level = 1,
+	.qos.qos_port = 1,
+	.links = master_qdss_bam_links,
+	.num_links = ARRAY_SIZE(master_qdss_bam_links),
+};
+
+static const u16 master_snoc_cfg_links[] = {
+	MSM8998_SLAVE_SRVC_SNOC,
+};
+
+static struct qcom_icc_node mas_snoc_cfg = {
+	.name = "master_snoc_cfg",
+	.id = MSM8998_MASTER_SNOC_CFG,
+	.buswidth = 16,
+	.mas_rpm_id = 20,
+	.slv_rpm_id = -1,
+	.links = master_snoc_cfg_links,
+	.num_links = ARRAY_SIZE(master_snoc_cfg_links),
+};
+
+static const u16 master_bimc_snoc_0_links[] = {
+	MSM8998_SLAVE_PIMEM,
+	MSM8998_SLAVE_LPASS,
+	MSM8998_SLAVE_HMSS,
+	MSM8998_SLAVE_WLAN,
+	MSM8998_SLAVE_SNOC_CNOC,
+	MSM8998_SLAVE_IMEM,
+	MSM8998_SLAVE_QDSS_STM,
+};
+
+static struct qcom_icc_node mas_bimc_snoc_0 = {
+	.name = "master_bimc_snoc_0",
+	.id = MSM8998_MASTER_BIMC_SNOC_0,
+	.buswidth = 16,
+	.mas_rpm_id = 21,
+	.slv_rpm_id = -1,
+	.links = master_bimc_snoc_0_links,
+	.num_links = ARRAY_SIZE(master_bimc_snoc_0_links),
+};
+
+static const u16 master_bimc_snoc_1_links[] = {
+	MSM8998_SLAVE_PCIE_0,
+};
+
+static struct qcom_icc_node mas_bimc_snoc_1 = {
+	.name = "master_bimc_snoc_1",
+	.id = MSM8998_MASTER_BIMC_SNOC_1,
+	.buswidth = 16,
+	.mas_rpm_id = 109,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = master_bimc_snoc_1_links,
+	.num_links = ARRAY_SIZE(master_bimc_snoc_1_links),
+};
+
+static const u16 master_a1noc_snoc_links[] = {
+	MSM8998_SLAVE_PIMEM,
+	MSM8998_SLAVE_PCIE_0,
+	MSM8998_SLAVE_LPASS,
+	MSM8998_SLAVE_HMSS,
+	MSM8998_SLAVE_SNOC_BIMC,
+	MSM8998_SLAVE_SNOC_CNOC,
+	MSM8998_SLAVE_IMEM,
+	MSM8998_SLAVE_QDSS_STM,
+};
+
+static struct qcom_icc_node mas_a1noc_snoc = {
+	.name = "master_a1noc_snoc",
+	.id = MSM8998_MASTER_A1NOC_SNOC,
+	.buswidth = 16,
+	.mas_rpm_id = 111,
+	.slv_rpm_id = -1,
+	.links = master_a1noc_snoc_links,
+	.num_links = ARRAY_SIZE(master_a1noc_snoc_links),
+};
+
+static const u16 master_a2noc_snoc_links[] = {
+	MSM8998_SLAVE_PIMEM,
+	MSM8998_SLAVE_PCIE_0,
+	MSM8998_SLAVE_LPASS,
+	MSM8998_SLAVE_HMSS,
+	MSM8998_SLAVE_SNOC_BIMC,
+	MSM8998_SLAVE_WLAN,
+	MSM8998_SLAVE_SNOC_CNOC,
+	MSM8998_SLAVE_IMEM,
+	MSM8998_SLAVE_QDSS_STM,
+};
+
+static struct qcom_icc_node mas_a2noc_snoc = {
+	.name = "master_a2noc_snoc",
+	.id = MSM8998_MASTER_A2NOC_SNOC,
+	.buswidth = 16,
+	.mas_rpm_id = 112,
+	.slv_rpm_id = -1,
+	.links = master_a2noc_snoc_links,
+	.num_links = ARRAY_SIZE(master_a2noc_snoc_links),
+};
+
+static const u16 master_qdss_etr_links[] = {
+	MSM8998_SLAVE_IMEM,
+	MSM8998_SLAVE_PIMEM,
+	MSM8998_SLAVE_SNOC_CNOC,
+	MSM8998_SLAVE_SNOC_BIMC,
+};
+
+static struct qcom_icc_node mas_qdss_etr = {
+	.name = "master_qdss_etr",
+	.id = MSM8998_MASTER_QDSS_ETR,
+	.buswidth = 16,
+	.mas_rpm_id = 31,
+	.slv_rpm_id = -1,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_FIXED,
+	.qos.areq_prio = 1,
+	.qos.prio_level = 1,
+	.qos.qos_port = 2,
+	.links = master_qdss_etr_links,
+	.num_links = ARRAY_SIZE(master_qdss_etr_links),
+};
+
+static const u16 slave_a1noc_snoc_links[] = {
+	MSM8998_MASTER_A1NOC_SNOC,
+};
+
+static struct qcom_icc_node slv_a1noc_snoc = {
+	.name = "slave_a1noc_snoc",
+	.id = MSM8998_SLAVE_A1NOC_SNOC,
+	.buswidth = 16,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 142,
+	.links = slave_a1noc_snoc_links,
+	.num_links = ARRAY_SIZE(slave_a1noc_snoc_links),
+};
+
+static const u16 slave_a2noc_snoc_links[] = {
+	MSM8998_MASTER_A2NOC_SNOC,
+};
+
+static struct qcom_icc_node slv_a2noc_snoc = {
+	.name = "slave_a2noc_snoc",
+	.id = MSM8998_SLAVE_A2NOC_SNOC,
+	.buswidth = 16,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 143,
+	.links = slave_a2noc_snoc_links,
+	.num_links = ARRAY_SIZE(slave_a2noc_snoc_links),
+};
+
+static struct qcom_icc_node slv_ebi = {
+	.name = "slave_ebi",
+	.id = MSM8998_SLAVE_EBI,
+	.channels = 2,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 0,
+};
+
+static struct qcom_icc_node slv_hmss_l3 = {
+	.name = "slave_hmss_l3",
+	.id = MSM8998_SLAVE_HMSS_L3,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 160,
+};
+
+static const u16 slave_bimc_snoc_0_links[] = {
+	MSM8998_MASTER_BIMC_SNOC_0,
+};
+
+static struct qcom_icc_node slv_bimc_snoc_0 = {
+	.name = "slave_bimc_snoc_0",
+	.id = MSM8998_SLAVE_BIMC_SNOC_0,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 2,
+	.links = slave_bimc_snoc_0_links,
+	.num_links = ARRAY_SIZE(slave_bimc_snoc_0_links),
+};
+
+static const u16 slave_bimc_snoc_1_links[] = {
+	MSM8998_MASTER_BIMC_SNOC_1,
+};
+
+static struct qcom_icc_node slv_bimc_snoc_1 = {
+	.name = "slave_bimc_snoc_1",
+	.id = MSM8998_SLAVE_BIMC_SNOC_1,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 138,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = slave_bimc_snoc_1_links,
+	.num_links = ARRAY_SIZE(slave_bimc_snoc_1_links),
+};
+
+static const u16 slave_cnoc_a2noc_links[] = {
+	MSM8998_MASTER_CNOC_A2NOC,
+};
+
+static struct qcom_icc_node slv_cnoc_a2noc = {
+	.name = "slave_cnoc_a2noc",
+	.id = MSM8998_SLAVE_CNOC_A2NOC,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 208,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = slave_cnoc_a2noc_links,
+	.num_links = ARRAY_SIZE(slave_cnoc_a2noc_links),
+};
+
+static struct qcom_icc_node slv_ssc_cfg = {
+	.name = "slave_ssc_cfg",
+	.id = MSM8998_SLAVE_SSC_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 177,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_mpm = {
+	.name = "slave_mpm",
+	.id = MSM8998_SLAVE_MPM,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 62,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_pmic_arb = {
+	.name = "slave_pmic_arb",
+	.id = MSM8998_SLAVE_PMIC_ARB,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 59,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_tlmm_north = {
+	.name = "slave_tlmm_north",
+	.id = MSM8998_SLAVE_TLMM_NORTH,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 214,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_pimem_cfg = {
+	.name = "slave_pimem_cfg",
+	.id = MSM8998_SLAVE_PIMEM_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 167,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_imem_cfg = {
+	.name = "slave_imem_cfg",
+	.id = MSM8998_SLAVE_IMEM_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 54,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_message_ram = {
+	.name = "slave_message_ram",
+	.id = MSM8998_SLAVE_MESSAGE_RAM,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 55,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_skl = {
+	.name = "slave_skl",
+	.id = MSM8998_SLAVE_SKL,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 196,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_bimc_cfg = {
+	.name = "slave_bimc_cfg",
+	.id = MSM8998_SLAVE_BIMC_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 56,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_prng = {
+	.name = "slave_prng",
+	.id = MSM8998_SLAVE_PRNG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 44,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_a2noc_cfg = {
+	.name = "slave_a2noc_cfg",
+	.id = MSM8998_SLAVE_A2NOC_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 150,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_ipa = {
+	.name = "slave_ipa",
+	.id = MSM8998_SLAVE_IPA,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 183,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_tcsr = {
+	.name = "slave_tcsr",
+	.id = MSM8998_SLAVE_TCSR,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 50,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_snoc_cfg = {
+	.name = "slave_snoc_cfg",
+	.id = MSM8998_SLAVE_SNOC_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 70,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_clk_ctl = {
+	.name = "slave_clk_ctl",
+	.id = MSM8998_SLAVE_CLK_CTL,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 47,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_glm = {
+	.name = "slave_glm",
+	.id = MSM8998_SLAVE_GLM,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 209,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_spdm = {
+	.name = "slave_spdm",
+	.id = MSM8998_SLAVE_SPDM,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 60,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_gpuss_cfg = {
+	.name = "slave_gpuss_cfg",
+	.id = MSM8998_SLAVE_GPUSS_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 11,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static const u16 slv_cnoc_mnoc_cfg_links[] = {
+	MSM8998_MASTER_CNOC_MNOC_CFG,
+};
+
+static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
+	.name = "slv_cnoc_mnoc_cfg",
+	.id = MSM8998_SLAVE_CNOC_MNOC_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 66,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = slv_cnoc_mnoc_cfg_links,
+	.num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links),
+};
+
+static struct qcom_icc_node slv_qm_cfg = {
+	.name = "slave_qm_cfg",
+	.id = MSM8998_SLAVE_QM_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 212,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_mss_cfg = {
+	.name = "slave_mss_cfg",
+	.id = MSM8998_SLAVE_MSS_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 48,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_ufs_cfg = {
+	.name = "slave_ufs_cfg",
+	.id = MSM8998_SLAVE_UFS_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 92,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_tlmm_west = {
+	.name = "slave_tlmm_west",
+	.id = MSM8998_SLAVE_TLMM_WEST,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 215,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_a1noc_cfg = {
+	.name = "slave_a1noc_cfg",
+	.id = MSM8998_SLAVE_A1NOC_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 147,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_ahb2phy = {
+	.name = "slave_ahb2phy",
+	.id = MSM8998_SLAVE_AHB2PHY,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 163,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_blsp_2 = {
+	.name = "slave_blsp_2",
+	.id = MSM8998_SLAVE_BLSP_2,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 37,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_pdm = {
+	.name = "slave_pdm",
+	.id = MSM8998_SLAVE_PDM,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 41,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_usb3_0 = {
+	.name = "slave_usb3_0",
+	.id = MSM8998_SLAVE_USB3_0,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 22,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_a1noc_smmu_cfg = {
+	.name = "slave_a1noc_smmu_cfg",
+	.id = MSM8998_SLAVE_A1NOC_SMMU_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 149,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_blsp_1 = {
+	.name = "slave_blsp_1",
+	.id = MSM8998_SLAVE_BLSP_1,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 39,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_sdcc_2 = {
+	.name = "slave_sdcc_2",
+	.id = MSM8998_SLAVE_SDCC_2,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 33,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_sdcc_4 = {
+	.name = "slave_sdcc_4",
+	.id = MSM8998_SLAVE_SDCC_4,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 34,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_tsif = {
+	.name = "slave_tsif",
+	.id = MSM8998_SLAVE_TSIF,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 35,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_qdss_cfg = {
+	.name = "slave_qdss_cfg",
+	.id = MSM8998_SLAVE_QDSS_CFG,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 63,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_tlmm_east = {
+	.name = "slave_tlmm_east",
+	.id = MSM8998_SLAVE_TLMM_EAST,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 213,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static const u16 slave_cnoc_mnoc_mmss_cfg_links[] = {
+	MSM8998_MASTER_CNOC_MNOC_MMSS_CFG,
+};
+
+static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
+	.name = "slave_cnoc_mnoc_mmss_cfg",
+	.id = MSM8998_SLAVE_CNOC_MNOC_MMSS_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 58,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = slave_cnoc_mnoc_mmss_cfg_links,
+	.num_links = ARRAY_SIZE(slave_cnoc_mnoc_mmss_cfg_links),
+};
+
+static struct qcom_icc_node slv_srvc_cnoc = {
+	.name = "slave_srvc_cnoc",
+	.id = MSM8998_SLAVE_SRVC_CNOC,
+	.buswidth = 4,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 76,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static const u16 slave_crvirt_a2noc_links[] = {
+	MSM8998_MASTER_CRVIRT_A2NOC,
+};
+
+static struct qcom_icc_node slv_crvirt_a2noc = {
+	.name = "slave_crvirt_a2noc",
+	.id = MSM8998_SLAVE_CRVIRT_A2NOC,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 207,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = slave_crvirt_a2noc_links,
+	.num_links = ARRAY_SIZE(slave_crvirt_a2noc_links),
+};
+
+static const u16 slave_gnoc_bimc_links[] = {
+	MSM8998_MASTER_GNOC_BIMC,
+};
+
+static struct qcom_icc_node slv_gnoc_bimc = {
+	.name = "slave_gnoc_bimc",
+	.id = MSM8998_SLAVE_GNOC_BIMC,
+	.buswidth = 32,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 210,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = slave_gnoc_bimc_links,
+	.num_links = ARRAY_SIZE(slave_gnoc_bimc_links),
+};
+
+static struct qcom_icc_node slv_camera_cfg = {
+	.name = "slave_camera_cfg",
+	.id = MSM8998_SLAVE_CAMERA_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 3,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_camera_throttle_cfg = {
+	.name = "slave_camera_throttle_cfg",
+	.id = MSM8998_SLAVE_CAMERA_THROTTLE_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 154,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_misc_cfg = {
+	.name = "slave_misc_cfg",
+	.id = MSM8998_SLAVE_MISC_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 8,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_venus_throttle_cfg = {
+	.name = "slave_venus_throttle_cfg",
+	.id = MSM8998_SLAVE_VENUS_THROTTLE_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 178,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_venus_cfg = {
+	.name = "slave_venus_cfg",
+	.id = MSM8998_SLAVE_VENUS_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 10,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_vmem_cfg = {
+	.name = "slave_vmem_cfg",
+	.id = MSM8998_SLAVE_VMEM_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 180,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_mmss_clk_xpu_cfg = {
+	.name = "slave_mmss_clk_xpu_cfg",
+	.id = MSM8998_SLAVE_MMSS_CLK_XPU_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 13,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_mmss_clk_cfg = {
+	.name = "slave_mmss_clk_cfg",
+	.id = MSM8998_SLAVE_MMSS_CLK_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 12,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_display_cfg = {
+	.name = "slave_display_cfg",
+	.id = MSM8998_SLAVE_DISPLAY_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 4,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_display_throttle_cfg = {
+	.name = "slave_display_throttle_cfg",
+	.id = MSM8998_SLAVE_DISPLAY_THROTTLE_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 156,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_smmu_cfg = {
+	.name = "slave_smmu_cfg",
+	.id = MSM8998_SLAVE_SMMU_CFG,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 205,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static const u16 slave_mnoc_bimc_links[] = {
+	MSM8998_MASTER_MNOC_BIMC,
+};
+
+static struct qcom_icc_node slv_mnoc_bimc = {
+	.name = "slave_mnoc_bimc",
+	.id = MSM8998_SLAVE_MNOC_BIMC,
+	.channels = 2,
+	.buswidth = 32,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 16,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+	.links = slave_mnoc_bimc_links,
+	.num_links = ARRAY_SIZE(slave_mnoc_bimc_links),
+};
+
+static struct qcom_icc_node slv_vmem = {
+	.name = "slave_vmem",
+	.id = MSM8998_SLAVE_VMEM,
+	.buswidth = 32,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 179,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_srvc_mnoc = {
+	.name = "slave_srvc_mnoc",
+	.id = MSM8998_SLAVE_SRVC_MNOC,
+	.buswidth = 8,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 17,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_hmss = {
+	.name = "slave_hmss",
+	.id = MSM8998_SLAVE_HMSS,
+	.buswidth = 16,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 20,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_lpass = {
+	.name = "slave_lpass",
+	.id = MSM8998_SLAVE_LPASS,
+	.buswidth = 16,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 21,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_wlan = {
+	.name = "slave_wlan",
+	.id = MSM8998_SLAVE_WLAN,
+	.buswidth = 16,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 206,
+};
+
+static const u16 slave_snoc_bimc_links[] = {
+	MSM8998_MASTER_SNOC_BIMC,
+};
+
+static struct qcom_icc_node slv_snoc_bimc = {
+	.name = "slave_snoc_bimc",
+	.id = MSM8998_SLAVE_SNOC_BIMC,
+	.channels = 2,
+	.buswidth = 32,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 24,
+	.links = slave_snoc_bimc_links,
+	.num_links = ARRAY_SIZE(slave_snoc_bimc_links),
+};
+
+static const u16 slave_snoc_cnoc_links[] = {
+	MSM8998_MASTER_SNOC_CNOC,
+};
+
+static struct qcom_icc_node slv_snoc_cnoc = {
+	.name = "slave_snoc_cnoc",
+	.id = MSM8998_SLAVE_SNOC_CNOC,
+	.buswidth = 16,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 25,
+	.links = slave_snoc_cnoc_links,
+	.num_links = ARRAY_SIZE(slave_snoc_cnoc_links),
+};
+
+static struct qcom_icc_node slv_imem = {
+	.name = "slave_imem",
+	.id = MSM8998_SLAVE_IMEM,
+	.buswidth = 16,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 26,
+};
+
+static struct qcom_icc_node slv_pimem = {
+	.name = "slave_pimem",
+	.id = MSM8998_SLAVE_PIMEM,
+	.buswidth = 16,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 166,
+};
+
+static struct qcom_icc_node slv_qdss_stm = {
+	.name = "slave_qdss_stm",
+	.id = MSM8998_SLAVE_QDSS_STM,
+	.buswidth = 16,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 30,
+};
+
+static struct qcom_icc_node slv_pcie_0 = {
+	.name = "slave_pcie_0",
+	.id = MSM8998_SLAVE_PCIE_0,
+	.buswidth = 16,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 84,
+	.qos.ap_owned = true,
+	.qos.qos_mode = NOC_QOS_MODE_INVALID,
+};
+
+static struct qcom_icc_node slv_srvc_snoc = {
+	.name = "slave_srvc_snoc",
+	.id = MSM8998_SLAVE_SRVC_SNOC,
+	.buswidth = 16,
+	.mas_rpm_id = -1,
+	.slv_rpm_id = 29,
+};
+
+static struct qcom_icc_node *msm8998_a1noc_nodes[] = {
+	[MASTER_PCIE_0] = &mas_pcie_0,
+	[MASTER_USB3] = &mas_usb3,
+	[MASTER_UFS] = &mas_ufs,
+	[MASTER_BLSP_2] = &mas_blsp_2,
+	[SLAVE_A1NOC_SNOC] = &slv_a1noc_snoc,
+};
+
+static const struct regmap_config msm8998_a1noc_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	/* 0x60000 downstream, but that would clash with SMMUs! */
+	.max_register	= 0x20000,
+	.fast_io	= true,
+};
+
+static struct qcom_icc_desc msm8998_a1noc = {
+	.type = QCOM_ICC_NOC,
+	.nodes = msm8998_a1noc_nodes,
+	.num_nodes = ARRAY_SIZE(msm8998_a1noc_nodes),
+	.regmap_cfg = &msm8998_a1noc_regmap_config,
+	.bus_clk_desc = &aggre1_clk,
+	.intf_clocks = a1noc_intf_clocks,
+	.num_intf_clocks = ARRAY_SIZE(a1noc_intf_clocks),
+	.qos_offset = 0x9000,
+};
+
+static struct qcom_icc_node *msm8998_a2noc_nodes[] = {
+	[MASTER_IPA] = &mas_ipa,
+	[MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc,
+	[MASTER_SDCC_2] = &mas_sdcc_2,
+	[MASTER_SDCC_4] = &mas_sdcc_4,
+	[MASTER_TSIF] = &mas_tsif,
+	[MASTER_BLSP_1] = &mas_blsp_1,
+	[MASTER_CRVIRT_A2NOC] = &mas_crvirt_a2noc,
+	[MASTER_CRYPTO_C0] = &mas_crypto,
+	[SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
+	[SLAVE_CRVIRT_A2NOC] = &slv_crvirt_a2noc,
+};
+
+static const struct regmap_config msm8998_a2noc_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	/* 0x60000 downstream, but that would clash with MNoC! */
+	.max_register	= 0x40000,
+	.fast_io	= true,
+};
+
+static struct qcom_icc_desc msm8998_a2noc = {
+	.type = QCOM_ICC_NOC,
+	.nodes = msm8998_a2noc_nodes,
+	.num_nodes = ARRAY_SIZE(msm8998_a2noc_nodes),
+	.regmap_cfg = &msm8998_a2noc_regmap_config,
+	.bus_clk_desc = &aggre2_clk,
+	.intf_clocks = a2noc_intf_clocks,
+	.num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
+	.qos_offset = 0x5000,
+};
+
+static struct qcom_icc_node *msm8998_bimc_nodes[] = {
+	[MASTER_GNOC_BIMC] = &mas_gnoc_bimc,
+	[MASTER_OXILI] = &mas_oxili,
+	[MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
+	[MASTER_SNOC_BIMC] = &mas_snoc_bimc,
+	[SLAVE_EBI] = &slv_ebi,
+	[SLAVE_HMSS_L3] = &slv_hmss_l3,
+	[SLAVE_BIMC_SNOC_0] = &slv_bimc_snoc_0,
+	[SLAVE_BIMC_SNOC_1] = &slv_bimc_snoc_1,
+};
+
+static const struct regmap_config msm8998_bimc_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	.max_register	= 0x80000,
+	.fast_io	= true,
+};
+
+static struct qcom_icc_desc msm8998_bimc = {
+	.type = QCOM_ICC_BIMC,
+	.nodes = msm8998_bimc_nodes,
+	.num_nodes = ARRAY_SIZE(msm8998_bimc_nodes),
+	.regmap_cfg = &msm8998_bimc_regmap_config,
+	/*
+	 * QoS offset is -0x300 (instead of 0x800 as one would expect) in this
+	 * case, as MSM8998 includes a peculiar design decision, where
+	 * what-would-be BIMC_BASE is really occupied by BWMON and then the
+	 * "useful" BWMON regs end right where BIMC_QoS begins.. But the driver
+	 * assumes we reserve BIMC_BASE and that the QPORT 0's register is at
+	 * (BIMC_BASE + QoS_OFFSET + 0x300), but that's what we unfortunately
+	 * have to treat as our BIMC_BASE in DT..
+	 */
+	.bus_clk_desc = &bimc_clk,
+	.qos_offset = -0x300,
+};
+
+static struct qcom_icc_node *msm8998_cnoc_nodes[] = {
+	[MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
+	[MASTER_QDSS_DAP] = &mas_qdss_dap,
+	[SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc,
+	[SLAVE_SSC_CFG] = &slv_ssc_cfg,
+	[SLAVE_MPM] = &slv_mpm,
+	[SLAVE_PMIC_ARB] = &slv_pmic_arb,
+	[SLAVE_TLMM_NORTH] = &slv_tlmm_north,
+	[SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
+	[SLAVE_IMEM_CFG] = &slv_imem_cfg,
+	[SLAVE_MESSAGE_RAM] = &slv_message_ram,
+	[SLAVE_SKL] = &slv_skl,
+	[SLAVE_BIMC_CFG] = &slv_bimc_cfg,
+	[SLAVE_PRNG] = &slv_prng,
+	[SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
+	[SLAVE_IPA] = &slv_ipa,
+	[SLAVE_TCSR] = &slv_tcsr,
+	[SLAVE_SNOC_CFG] = &slv_snoc_cfg,
+	[SLAVE_CLK_CTL] = &slv_clk_ctl,
+	[SLAVE_GLM] = &slv_glm,
+	[SLAVE_SPDM] = &slv_spdm,
+	[SLAVE_GPUSS_CFG] = &slv_gpuss_cfg,
+	[SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
+	[SLAVE_QM_CFG] = &slv_qm_cfg,
+	[SLAVE_MSS_CFG] = &slv_mss_cfg,
+	[SLAVE_UFS_CFG] = &slv_ufs_cfg,
+	[SLAVE_TLMM_WEST] = &slv_tlmm_west,
+	[SLAVE_A1NOC_CFG] = &slv_a1noc_cfg,
+	[SLAVE_AHB2PHY] = &slv_ahb2phy,
+	[SLAVE_BLSP_2] = &slv_blsp_2,
+	[SLAVE_PDM] = &slv_pdm,
+	[SLAVE_USB3_0] = &slv_usb3_0,
+	[SLAVE_A1NOC_SMMU_CFG] = &slv_a1noc_smmu_cfg,
+	[SLAVE_BLSP_1] = &slv_blsp_1,
+	[SLAVE_SDCC_2] = &slv_sdcc_2,
+	[SLAVE_SDCC_4] = &slv_sdcc_4,
+	[SLAVE_TSIF] = &slv_tsif,
+	[SLAVE_QDSS_CFG] = &slv_qdss_cfg,
+	[SLAVE_TLMM_EAST] = &slv_tlmm_east,
+	[SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
+	[SLAVE_SRVC_CNOC] = &slv_srvc_cnoc,
+};
+
+static const struct regmap_config msm8998_cnoc_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	.max_register	= 0x10000,
+	.fast_io	= true,
+};
+
+static struct qcom_icc_desc msm8998_cnoc = {
+	.type = QCOM_ICC_NOC,
+	.nodes = msm8998_cnoc_nodes,
+	.num_nodes = ARRAY_SIZE(msm8998_cnoc_nodes),
+	.regmap_cfg = &msm8998_cnoc_regmap_config,
+	.bus_clk_desc = &bus_2_clk,
+	.intf_clocks = cnoc_snoc_intf_clocks,
+	.num_intf_clocks = ARRAY_SIZE(cnoc_snoc_intf_clocks),
+	.keep_alive = true,
+};
+
+static struct qcom_icc_node *msm8998_gnoc_nodes[] = {
+	[MASTER_APSS_PROC] = &mas_apss_proc,
+	[SLAVE_GNOC_BIMC] = &slv_gnoc_bimc,
+};
+
+static const struct regmap_config msm8998_gnoc_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	.max_register	= 0x10000,
+	.fast_io	= true,
+};
+
+static struct qcom_icc_desc msm8998_gnoc = {
+	.type = QCOM_ICC_NOC,
+	.nodes = msm8998_gnoc_nodes,
+	.num_nodes = ARRAY_SIZE(msm8998_gnoc_nodes),
+	.regmap_cfg = &msm8998_gnoc_regmap_config,
+};
+
+static struct qcom_icc_node *msm8998_mnoc_nodes[] = {
+	[MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
+	[MASTER_CPP] = &mas_cpp,
+	[MASTER_JPEG] = &mas_jpeg,
+	[MASTER_MDP_P0] = &mas_mdp_p0,
+	[MASTER_MDP_P1] = &mas_mdp_p1,
+	[MASTER_ROTATOR] = &mas_rotator,
+	[MASTER_VENUS] = &mas_venus,
+	[MASTER_VFE] = &mas_vfe,
+	[MASTER_VENUS_VMEM] = &mas_venus_vmem,
+	[SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
+	[SLAVE_VMEM] = &slv_vmem,
+	[SLAVE_SRVC_MNOC] = &slv_srvc_mnoc,
+};
+
+static const struct regmap_config msm8998_mnoc_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	.max_register	= 0x10000,
+	.fast_io	= true,
+};
+
+static struct qcom_icc_desc msm8998_mnoc = {
+	.type = QCOM_ICC_NOC,
+	.nodes = msm8998_mnoc_nodes,
+	.num_nodes = ARRAY_SIZE(msm8998_mnoc_nodes),
+	.regmap_cfg = &msm8998_mnoc_regmap_config,
+	.bus_clk_desc = &mmaxi_0_clk,
+	.intf_clocks = mnoc_intf_clocks,
+	.num_intf_clocks = ARRAY_SIZE(mnoc_intf_clocks),
+	.qos_offset = 0x4000,
+};
+
+static struct qcom_icc_node *msm8998_mnoc_ahb_nodes[] = {
+	[MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
+	[SLAVE_CAMERA_CFG] = &slv_camera_cfg,
+	[SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
+	[SLAVE_MISC_CFG] = &slv_misc_cfg,
+	[SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
+	[SLAVE_VENUS_CFG] = &slv_venus_cfg,
+	[SLAVE_VMEM_CFG] = &slv_vmem_cfg,
+	[SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
+	[SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
+	[SLAVE_DISPLAY_CFG] = &slv_display_cfg,
+	[SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
+	[SLAVE_SMMU_CFG] = &slv_smmu_cfg,
+};
+
+static struct qcom_icc_desc msm8998_mnoc_ahb = {
+	.type = QCOM_ICC_NOC,
+	.nodes = msm8998_mnoc_ahb_nodes,
+	.num_nodes = ARRAY_SIZE(msm8998_mnoc_ahb_nodes),
+	.regmap_cfg = &msm8998_mnoc_regmap_config,
+};
+
+static struct qcom_icc_node *msm8998_snoc_nodes[] = {
+	[MASTER_HMSS] = &mas_hmss,
+	[MASTER_QDSS_BAM] = &mas_qdss_bam,
+	[MASTER_SNOC_CFG] = &mas_snoc_cfg,
+	[MASTER_BIMC_SNOC_0] = &mas_bimc_snoc_0,
+	[MASTER_BIMC_SNOC_1] = &mas_bimc_snoc_1,
+	[MASTER_A1NOC_SNOC] = &mas_a1noc_snoc,
+	[MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
+	[MASTER_QDSS_ETR] = &mas_qdss_etr,
+	[SLAVE_HMSS] = &slv_hmss,
+	[SLAVE_LPASS] = &slv_lpass,
+	[SLAVE_WLAN] = &slv_wlan,
+	[SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
+	[SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
+	[SLAVE_IMEM] = &slv_imem,
+	[SLAVE_PIMEM] = &slv_pimem,
+	[SLAVE_QDSS_STM] = &slv_qdss_stm,
+	[SLAVE_PCIE_0] = &slv_pcie_0,
+	[SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
+};
+
+static const struct regmap_config msm8998_snoc_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	.max_register	= 0x40000,
+	.fast_io	= true,
+};
+
+static struct qcom_icc_desc msm8998_snoc = {
+	.type = QCOM_ICC_NOC,
+	.nodes = msm8998_snoc_nodes,
+	.num_nodes = ARRAY_SIZE(msm8998_snoc_nodes),
+	.regmap_cfg = &msm8998_snoc_regmap_config,
+	.bus_clk_desc = &bus_1_clk,
+	.intf_clocks = cnoc_snoc_intf_clocks,
+	.num_intf_clocks = ARRAY_SIZE(cnoc_snoc_intf_clocks),
+	.qos_offset = 0x5000,
+};
+
+static const struct of_device_id qnoc_of_match[] = {
+	{ .compatible = "qcom,msm8998-a1noc", .data = &msm8998_a1noc },
+	{ .compatible = "qcom,msm8998-a2noc", .data = &msm8998_a2noc },
+	{ .compatible = "qcom,msm8998-bimc", .data = &msm8998_bimc },
+	{ .compatible = "qcom,msm8998-cnoc", .data = &msm8998_cnoc },
+	{ .compatible = "qcom,msm8998-mnoc", .data = &msm8998_mnoc },
+	{ .compatible = "qcom,msm8998-mnoc-ahb", .data = &msm8998_mnoc_ahb },
+	{ .compatible = "qcom,msm8998-gnoc", .data = &msm8998_gnoc },
+	{ .compatible = "qcom,msm8998-snoc", .data = &msm8998_snoc },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, qnoc_of_match);
+
+static struct platform_driver qnoc_driver = {
+	.probe = qnoc_probe,
+	.remove = qnoc_remove,
+	.driver = {
+		.name = "qnoc-msm8998",
+		.of_match_table = qnoc_of_match,
+		.sync_state = icc_sync_state,
+	},
+};
+static int __init qnoc_driver_init(void)
+{
+	return platform_driver_register(&qnoc_driver);
+}
+core_initcall(qnoc_driver_init);
+
+static void __exit qnoc_driver_exit(void)
+{
+	platform_driver_unregister(&qnoc_driver);
+}
+module_exit(qnoc_driver_exit);
+
+MODULE_DESCRIPTION("MSM8998 NoC driver");
+MODULE_LICENSE("GPL");

-- 
2.47.3

[PATCH 7/8] arm64: dts: qcom: msm8998: add interconnect provider nodes

[Dmitry Baryshkov]

MSM8998 has an interconnect provider driver, but the SoC device tree
describes none of the NoC devices it binds to, so no bus bandwidth or
NoC clock scaling is possible and every consumer that wants to vote is
left without a provider.

Add the eight NoC nodes.  The AHB MMSS NoC shares its register space
with the MMSS NoC and is described as its child.  The A1NoC and A2NoC
register ranges are shrunk compared to the downstream ones, which
overlap the SMMU and the MMSS NoC respectively.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/msm8998.dtsi | 89 +++++++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index bd8b69e323e1..bb004e0b74ef 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/interconnect/qcom,msm8998.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/gpio/gpio.h>
 
@@ -859,6 +860,13 @@ qusb2_hstx_trim: hstx-trim@23a {
 			};
 		};
 
+		bimc: interconnect@1008300 {
+			compatible = "qcom,msm8998-bimc";
+			reg = <0x01008300 0x77d00>;
+
+			#interconnect-cells = <2>;
+		};
+
 		tsens0: thermal@10ab000 {
 			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 			reg = <0x010ab000 0x1000>, /* TM */
@@ -881,6 +889,42 @@ tsens1: thermal@10ae000 {
 			#thermal-sensor-cells = <1>;
 		};
 
+		cnoc: interconnect@1500000 {
+			compatible = "qcom,msm8998-cnoc";
+			reg = <0x01500000 0x10000>;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>;
+			clock-names = "iface";
+
+			#interconnect-cells = <2>;
+		};
+
+		snoc: interconnect@1620000 {
+			compatible = "qcom,msm8998-snoc";
+			reg = <0x01620000 0x40000>;
+
+			clocks = <&gcc GCC_MMSS_SYS_NOC_AXI_CLK>;
+			clock-names = "iface";
+
+			#interconnect-cells = <2>;
+		};
+
+		a1noc: interconnect@1660000 {
+			compatible = "qcom,msm8998-a1noc";
+			reg = <0x01660000 0x20000>;
+
+			clocks = <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
+				 <&gcc GCC_UFS_AXI_CLK>,
+				 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "aggre1_ufs_axi",
+				      "ufs_axi",
+				      "usb_axi",
+				      "blsp2_ahb";
+
+			#interconnect-cells = <2>;
+		};
+
 		anoc1_smmu: iommu@1680000 {
 			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
 			reg = <0x01680000 0x10000>;
@@ -915,6 +959,43 @@ anoc2_smmu: iommu@16c0000 {
 				<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
 		};
 
+		a2noc: interconnect@1700000 {
+			compatible = "qcom,msm8998-a2noc";
+			reg = <0x01700000 0x40000>;
+
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC4_AHB_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>,
+				 <&rpmcc RPM_SMD_IPA_CLK>;
+			clock-names = "sdcc2_ahb",
+				      "sdcc4_ahb",
+				      "blsp1_ahb",
+				      "ipa";
+
+			#interconnect-cells = <2>;
+		};
+
+		mnoc: interconnect@1740000 {
+			compatible = "qcom,msm8998-mnoc";
+			reg = <0x01740000 0x10000>;
+
+			clocks = <&mmcc MNOC_AHB_CLK>,
+				 <&mmcc MNOC_MAXI_CLK>;
+			clock-names = "iface",
+				      "mnoc_bus";
+
+			#interconnect-cells = <2>;
+
+			mnoc_ahb: interconnect-mnoc-ahb {
+				compatible = "qcom,msm8998-mnoc-ahb";
+
+				clocks = <&mmcc AHB_CLK_SRC>;
+				clock-names = "bus";
+
+				#interconnect-cells = <2>;
+			};
+		};
+
 		pcie0: pcie@1c00000 {
 			compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
 			reg = <0x01c00000 0x2000>,
@@ -3181,6 +3262,7 @@ venus: video-codec@cc00000 {
 				 <&mmcc VIDEO_AXI_CLK>,
 				 <&mmcc VIDEO_MAXI_CLK>;
 			clock-names = "core", "iface", "bus", "mbus";
+
 			iommus = <&mmss_smmu 0x400>,
 				 <&mmss_smmu 0x401>,
 				 <&mmss_smmu 0x40a>,
@@ -3290,6 +3372,13 @@ glink-edge {
 			};
 		};
 
+		gnoc: interconnect@17900000 {
+			compatible = "qcom,msm8998-gnoc";
+			reg = <0x17900000 0x10000>;
+
+			#interconnect-cells = <2>;
+		};
+
 		apcs_glb: mailbox@17911000 {
 			compatible = "qcom,msm8998-apcs-hmss-global",
 				     "qcom,msm8994-apcs-kpss-global";

-- 
2.47.3

[PATCH 8/8] arm64: dts: qcom: msm8998: wire up interconnect paths

[Dmitry Baryshkov]

With the NoC providers described but no consumer referencing them, the
NoC bus clocks stay at their boot rates: nothing votes for DDR or
config bandwidth, so masters such as MDSS or UFS run on whatever the
bootloader left behind.

Add the interconnect paths for the GPU, MDSS, Venus, UFS, USB and SDHC2.
PCIe is deliberately left out: MSM8998 has no route from the CPU to the
PCIe config slave, and requesting one only makes the PCIe driver fail
to probe.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/msm8998.dtsi | 38 +++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index bb004e0b74ef..939601322cfb 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,msm8998.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -1093,6 +1094,12 @@ ufshc: ufshc@1da4000 {
 			compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
 			reg = <0x01da4000 0x2500>;
 			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&a1noc MASTER_UFS QCOM_ICC_TAG_ALWAYS
+					 &bimc SLAVE_EBI QCOM_ICC_TAG_ALWAYS>,
+					<&gnoc MASTER_APSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &cnoc SLAVE_UFS_CFG QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "ufs-ddr", "cpu-ufs";
+
 			phys = <&ufsphy>;
 			phy-names = "ufsphy";
 			lanes-per-direction = <2>;
@@ -1622,6 +1629,10 @@ adreno_gpu: gpu@5000000 {
 				"rbcpr",
 				"core";
 
+			interconnects = <&bimc MASTER_OXILI QCOM_ICC_TAG_ALWAYS
+					 &bimc SLAVE_EBI QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "gfx-mem";
+
 			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 			iommus = <&adreno_smmu 0>;
 			operating-points-v2 = <&gpu_opp_table>;
@@ -2276,6 +2287,12 @@ usb3: usb@a8f8800 {
 				      "sleep",
 				      "mock_utmi";
 
+			interconnects = <&a1noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS
+					 &bimc SLAVE_EBI QCOM_ICC_TAG_ALWAYS>,
+					<&gnoc MASTER_APSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &cnoc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
 			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 					  <&gcc GCC_USB30_MASTER_CLK>;
 			assigned-clock-rates = <19200000>, <120000000>;
@@ -2355,6 +2372,12 @@ sdhc2: mmc@c0a4900 {
 				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
 
+			interconnects = <&a2noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+					 &bimc SLAVE_EBI QCOM_ICC_TAG_ALWAYS>,
+					<&gnoc MASTER_APSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &cnoc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "sdhc-ddr", "cpu-sdhc";
+
 			clock-names = "iface", "core", "xo";
 			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 				 <&gcc GCC_SDCC2_APPS_CLK>,
@@ -2914,6 +2937,16 @@ mdss: display-subsystem@c900000 {
 				      "bus",
 				      "core";
 
+			interconnects = <&mnoc MASTER_MDP_P0 QCOM_ICC_TAG_ALWAYS
+					 &bimc SLAVE_EBI QCOM_ICC_TAG_ALWAYS>,
+					<&mnoc MASTER_MDP_P1 QCOM_ICC_TAG_ALWAYS
+					 &bimc SLAVE_EBI QCOM_ICC_TAG_ALWAYS>,
+					<&gnoc MASTER_APSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &mnoc_ahb SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "mdp0-mem",
+					     "mdp1-mem",
+					     "cpu-cfg";
+
 			power-domains = <&mmcc MDSS_GDSC>;
 			iommus = <&mmss_smmu 0>;
 
@@ -3263,6 +3296,11 @@ venus: video-codec@cc00000 {
 				 <&mmcc VIDEO_MAXI_CLK>;
 			clock-names = "core", "iface", "bus", "mbus";
 
+			interconnects = <&mnoc MASTER_VENUS QCOM_ICC_TAG_ALWAYS
+					 &bimc SLAVE_EBI QCOM_ICC_TAG_ALWAYS>,
+					<&gnoc MASTER_APSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &mnoc_ahb SLAVE_VENUS_CFG QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "video-mem", "cpu-cfg";
 			iommus = <&mmss_smmu 0x400>,
 				 <&mmss_smmu 0x401>,
 				 <&mmss_smmu 0x40a>,

-- 
2.47.3

Re: [PATCH 7/8] arm64: dts: qcom: msm8998: add interconnect provider nodes

[Konrad Dybcio]

On 10/19/26 4:12 PM, Dmitry Baryshkov wrote:
> MSM8998 has an interconnect provider driver, but the SoC device tree
> describes none of the NoC devices it binds to, so no bus bandwidth or
> NoC clock scaling is possible and every consumer that wants to vote is
> left without a provider.
> 
> Add the eight NoC nodes.  The AHB MMSS NoC shares its register space
> with the MMSS NoC and is described as its child.  The A1NoC and A2NoC
> register ranges are shrunk compared to the downstream ones, which
> overlap the SMMU and the MMSS NoC respectively.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 8/8] arm64: dts: qcom: msm8998: wire up interconnect paths

[Konrad Dybcio]

On 10/19/26 4:12 PM, Dmitry Baryshkov wrote:
> With the NoC providers described but no consumer referencing them, the
> NoC bus clocks stay at their boot rates: nothing votes for DDR or
> config bandwidth, so masters such as MDSS or UFS run on whatever the
> bootloader left behind.
> 
> Add the interconnect paths for the GPU, MDSS, Venus, UFS, USB and SDHC2.
> PCIe is deliberately left out: MSM8998 has no route from the CPU to the
> PCIe config slave, and requesting one only makes the PCIe driver fail
> to probe.

On upstream, sm8450 is the first one to have one wired up in DT
(intriguing), sdm845 is the first one to have one in the icc driver

Downstream, 8450 and earlier do not have a path defined on the PCIe
node but clearly that relies on lucky ordering

I threw the LLM at msm8998-bus.dtsi and it said:

The only edges into slv_pcie_0 come from three masters:
- mas_bimc_snoc_1 (line 669), reachable only from slv_bimc_snoc_1,
  which is fed by mas_oxili and mas_mnoc_bimc. Neither is reachable from
  the apps master.
- mas_a1noc_snoc (line 679), reachable only from slv_a1noc_snoc, which
  is fed by PCIe, USB3, UFS, and BLSP2 masters.
- mas_a2noc_snoc (line 692), reachable only from slv_a2noc_snoc, which
  is fed by mas_cnoc_a2noc, IPA, SDCC2/4, TSIF, BLSP1, and
  mas_cr_virt_a2noc. The last two come from slv_cnoc_a2noc (fed only by
  mas_qdss_dap) and slv_cr_virt_a2noc (fed only by mas_crypto_c0). Neither
  of those is reachable from the apps master.

But I wonder if it's some sort of an oversight. Can we try to
regenerate the paths internally?

Konrad

Re: [PATCH 1/8] dt-bindings: interconnect: add Qualcomm MSM8998 NoC

[Krzysztof Kozlowski]

On Mon, Oct 19, 2026 at 05:12:39PM +0300, Dmitry Baryshkov wrote:
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,msm8998-a1noc
> +      - qcom,msm8998-a2noc
> +      - qcom,msm8998-bimc
> +      - qcom,msm8998-cnoc
> +      - qcom,msm8998-gnoc
> +      - qcom,msm8998-mnoc
> +      - qcom,msm8998-mnoc-ahb
> +      - qcom,msm8998-snoc
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 4
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 4

...


> +  - if:
> +      properties:
> +        compatible:
> +          const: qcom,msm8998-mnoc-ahb
> +
> +    then:
> +      description:
> +        The MMSS AHB NoC shares its register space with the MMSS NoC, so it is
> +        described as a child of the latter and has no register range of its own.
> +
> +      properties:

reg: false

> +        clocks:
> +          items:
> +            - description: MMSS AHB Clock
> +
> +        clock-names:
> +          const: bus
> +
> +      required:
> +        - clocks
> +        - clock-names
> +
> +    else:
> +      required:
> +        - reg
> +
> +  - if:
> +      properties:
> +        compatible:
> +          enum:
> +            - qcom,msm8998-bimc
> +            - qcom,msm8998-gnoc
> +
> +    then:
> +      properties:
> +        clocks: false
> +        clock-names: false
> +

unevaluatedProperties should go here, just before the example

> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,gcc-msm8998.h>
> +    #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
> +
> +    interconnect@1008300 {
> +        compatible = "qcom,msm8998-bimc";
> +        reg = <0x01008300 0x77d00>;
> +        #interconnect-cells = <2>;
> +    };
> +
> +    interconnect@1740000 {
> +        compatible = "qcom,msm8998-mnoc";
> +        reg = <0x01740000 0x10000>;
> +        clocks = <&mmcc MNOC_AHB_CLK>, <&mmcc MNOC_MAXI_CLK>;
> +        clock-names = "iface", "mnoc_bus";
> +        #interconnect-cells = <2>;
> +
> +        interconnect-mnoc-ahb {

I do not see how this can validate. You do not allow any children in
your binding. Your tpo-level properties should define all possible
properties and nodes.

also, name should be just "interconnect"


Best regards,
Krzysztof