[PATCH 1/2] dt-bindings: gpio: fairchild,74hc595: add support for nxp,74lv164

[PATCH 1/2] dt-bindings: gpio: fairchild,74hc595: add support for nxp,74lv164

[Christian Marangi]

Document support for nxp,74lv164 as a variant of the currently supported
8-bit shift register with the only difference of not having an Output
Enable pin and a simulated Chip Select pin.

These basic 8-bit shift register chips directly change the outputs as bits
are shifted in. Particularly used to handle multiple LED for basic state
feedback.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 .../bindings/gpio/fairchild,74hc595.yaml       | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml
index 451538df63f7..0d5596af0ced 100644
--- a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml
+++ b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml
@@ -7,9 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Generic 8-bit shift register
 
 description: |
-  NOTE: These chips nominally don't have a chip select pin. They do however
-  have a rising-edge triggered latch clock (or storage register clock) pin,
-  which behaves like an active-low chip select.
+  NOTE: These chips nominally don't have a chip select pin. 59x chip family
+  do however have a rising-edge triggered latch clock (or storage register
+  clock) pin, which behaves like an active-low chip select.
 
   After the bits are shifted into the shift register, CS# is driven high, which
   the 74HC595 sees as a rising edge on the latch clock that results in a
@@ -22,6 +22,9 @@ description: |
                  ___                     ________
   chip select#      |___________________|
 
+  Other chip family (namely 164) directly change the outputs as bits are shifted
+  in.
+
 maintainers:
   - Maxime Ripard <mripard@kernel.org>
 
@@ -29,6 +32,7 @@ properties:
   compatible:
     enum:
       - fairchild,74hc595
+      - nxp,74lv164
       - nxp,74lvc594
 
   reg:
@@ -76,6 +80,14 @@ required:
 
 allOf:
   - $ref: /schemas/spi/spi-peripheral-props.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nxp,74lv164
+    then:
+      properties:
+        enable-gpios: false
 
 unevaluatedProperties: false
 
-- 
2.55.0

[PATCH 2/2] gpio: 74x164: add support for 74lv164 shift register variant

[Christian Marangi]

Add compatible and spi define to support 74lv164 shift register variant.
These work the same way as the 59x chip family with the only difference of
not having a "storage" feature by directly changing the outputs as bits are
shifted in without having to toggle extra pins.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/gpio/gpio-74x164.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpio/gpio-74x164.c b/drivers/gpio/gpio-74x164.c
index 5ca61cf5206a..46562c348c9c 100644
--- a/drivers/gpio/gpio-74x164.c
+++ b/drivers/gpio/gpio-74x164.c
@@ -181,6 +181,7 @@ static int gen_74x164_probe(struct spi_device *spi)
 
 static const struct spi_device_id gen_74x164_spi_ids[] = {
 	{ .name = "74hc595" },
+	{ .name = "74lv164" },
 	{ .name = "74lvc594" },
 	{},
 };
@@ -188,6 +189,7 @@ MODULE_DEVICE_TABLE(spi, gen_74x164_spi_ids);
 
 static const struct of_device_id gen_74x164_dt_ids[] = {
 	{ .compatible = "fairchild,74hc595" },
+	{ .compatible = "nxp,74lv164" },
 	{ .compatible = "nxp,74lvc594" },
 	{},
 };
-- 
2.55.0