Re: [PATCH v3 8/8] iio: adc: rzt2h: Add support for RZ/V2H(P) SoC

[Jonathan Cameron <jic23@kernel.org>]

On Sat, 24 Oct 2026 13:38:27 +0300
Andy Shevchenko <andriy.shevchenko@intel.com> wrote:

> On Fri, Oct 23, 2026 at 06:59:19PM +0100, Prabhakar wrote:
> 
> > Add support for the ADC found on the Renesas RZ/V2H(P) SoC, which shares
> > the RZ/T2H ADC IP but differs in channel count, sampling, calibration and
> > resolution support.
> > 
> > The RZ/V2H(P) ADC provides 8 channels, has a fixed conversion time of
> > 20 ADCLK cycles, does not support calibration, and supports selectable
> > 12-bit and 8-bit conversion resolution.
> > 
> > Expose the fixed sampling frequency as a read-only attribute and allow
> > the conversion resolution to be changed through the scale attribute.
> > Use extended scan types so the reported scan type follows the selected
> > resolution, and prevent resolution changes while buffered capture is
> > active.  
> 
> ...
> 
> > +static int rzt2h_adc_write_scale(struct iio_dev *indio_dev,
> > +				 struct iio_chan_spec const *chan,
> > +				 int val, int val2)
> > +{
> > +	struct rzt2h_adc *adc = iio_priv(indio_dev);
> > +	u64 req_scale, scale;
> > +	unsigned int i;
> > +
> > +	if (!(adc->chip_info->features & RZT2H_ADC_FEATURE_RES_SELECT))
> > +		return -EINVAL;
> > +
> > +	req_scale = mul_u32_u32(val, NANO) + val2;  
> 
> But what's wrong with the simple 1ULL * val * NANO?
> 
> > +	for (i = 0; i < chan->num_ext_scan_type; i++) {
> > +		scale = mul_u32_u32(RZT2H_ADC_VREF_mV, NANO) >>  
> 
> Similar Q.

Patch on top please - I might squash it with original.

Thanks,

Jonathan

> 
> > +			chan->ext_scan_type[i].realbits;
> > +		if (scale == req_scale)
> > +			break;
> > +	}
> > +	if (i == chan->num_ext_scan_type)
> > +		return -EINVAL;
> > +
> > +	/* The scan type changes with the resolution. */
> > +	IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
> > +	if (IIO_DEV_ACQUIRE_FAILED(claim))
> > +		return -EBUSY;
> > +
> > +	adc->resolution = i;
> > +
> > +	return 0;
> > +}  
>