Re: [PATCH DNM v3 8/8] arm64: dts: qcom: kaanapali: Add MPAM MSC nodes for the L2 caches

[Rob Herring <robh@kernel.org>]

On Fri, Oct 23, 2026 at 02:03:57PM +0200, Konrad Dybcio wrote:
> On 10/14/26 9:09 AM, Yin Li wrote:
> > 
> > 
> > On 10/13/2026 6:37 PM, Ben Horgan wrote:
> >> Hi Yin,
> 
> [...]
> 
> > Hi Ben, Konrad,
> > 
> > The original 0x10000 reflects the per-MSC register block size as
> > allocated in the KNP hardware — as Konrad noted, Qualcomm DTs tend to
> > use "how much register space is allocated for this block" rather than
> > "what the last used register ends" to avoid holes.
> > 
> > We'd like to update it to 0x321c to give other platform authors a more useful reference, without exposing KNP-internal details such as address holes between blocks. In our case, we don't implement MPAMCFG_MBW_PBM, and — as you noted — the registers from 0x3000 onward are domain-specific; since we have no domains, those aren't used either. So the actual footprint we need is smaller than 0x321c, but showing the full 0x321c gives other authors a complete picture of the allocated register space.
> > 
> > That said, this patch is marked DNM and is intended as a local
> > verification example only, not for merging.
> 
> If you don't intend it to get merged, you can even put 0x12345
> in there. But for future submissions that will have the intent to
> be merged, please stick to the 0x10000 size

Why? That just wastes virtual memory space. I know it is "infinite" on 
64-bit and *only* 96 bytes of PTEs, but still.

Rob