[PATCH 0/6] MIPS: Ingenic: Add XBurst / XBurst II infrastructure and SoC support

[PATCH 0/6] MIPS: Ingenic: Add XBurst / XBurst II infrastructure and SoC support

[H. Nikolaus Schaller]

PATCH V1 2026-10-25 20:20:55:
The series updates the Ingenic platform support to allow clean transitions
between bootloader-provided Device Trees and built-in fallbacks. It provides
the foundational Kconfig, PRID, and CPU-probe blocks required for newer 
Ingenic/Lumissil hardware generations (X1600, X2000, X2600).

The first patch corrects an inverted Kconfig condition regarding appended 
and built-in DTBs. This fix is necessary to allow configurations where 
the kernel relies entirely on a Device Tree provided dynamically by the 
bootloader instead of forcing a built-in fallback.

The remaining patches implement CPU-probe initialization, correct PRID 
mappings (including vendor-kernel values for the Ingenic A1 SoC), 
platform load addresses, Kconfig updates, and generic board match updates.

Structure of the series:
1. MIPS: Ingenic: Fix inverted MIPS_NO_APPENDED_DTB logic in Kconfig
2. MIPS: Ingenic: Add and update PRIDs for XBurst II R0 and R2
3. MIPS: Ingenic: Expand Kconfig for X1600, X2000, and X2600 SoCs
4. MIPS: Ingenic: Add cpu-probe setup for XBurst and XBurst II R2
5. MIPS: generic: Add MACH_INGENIC type and compatible for X1600
6. MIPS: Ingenic: Add Platform makefile for X1600 and X2000

Testing:
The series has been compile-tested for generic Ingenic targets. PRID 
values for jz4780, x1600, X2000, X2600 were verified on real hardware 
(CI20, LX16, LX20 and LX26 boards respectively).

Please review and consider for inclusion.


H. Nikolaus Schaller (6):
  MIPS: Ingenic: Fix inverted MIPS_NO_APPENDED_DTB logic in Kconfig
  MIPS: Ingenic: Add and update PRIDs for XBurst II R0 and R2
  MIPS: Ingenic: Add cpu-probe setup for XBurst and XBurst II R2
  MIPS: generic: Add MACH_INGENIC type and compatible for X1600
  MIPS: Ingenic: Expand Kconfig for X1600, X2000, and X2600 SoCs
  MIPS: Ingenic: Add Platform makefile for X1600 and X2000

 arch/mips/Kconfig                 |  2 +-
 arch/mips/generic/board-ingenic.c |  3 +++
 arch/mips/include/asm/bootinfo.h  |  1 +
 arch/mips/include/asm/cpu.h       |  8 ++++---
 arch/mips/ingenic/Kconfig         | 35 ++++++++++++++++++++++++++++++-
 arch/mips/ingenic/Platform        |  2 ++
 arch/mips/kernel/cpu-probe.c      | 14 +++++++++++++
 7 files changed, 60 insertions(+), 5 deletions(-)
 create mode 100644 arch/mips/ingenic/Platform

-- 
2.56.0

[PATCH 1/6] MIPS: Ingenic: Fix inverted MIPS_NO_APPENDED_DTB logic in Kconfig

[H. Nikolaus Schaller]

Correct the inverted conditional selection of BUILTIN_DTB for
MACH_INGENIC.

Currently, the Kconfig logic forcefully selects BUILTIN_DTB when
MIPS_NO_APPENDED_DTB is enabled (i.e., when no DTB should be appended
to the image). This unintended behavior prevents turning off the
built-in DTB fallback, which is required when the kernel should use
a DTB provided directly by the bootloader.

Fix this by reversing the polarity using the logical NOT operator.

Fixes: f0f4a753079c ("MIPS: generic: Add support for Ingenic SoCs")
Fixes: 15205fc05482 ("MIPS: ingenic: Add support for appended devicetree")
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
 arch/mips/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d7c67cebe065f..702e2cde68eba 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -128,7 +128,7 @@ config MACH_INGENIC
 	select GPIOLIB
 	select COMMON_CLK
 	select GENERIC_IRQ_CHIP
-	select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
+	select BUILTIN_DTB if !MIPS_NO_APPENDED_DTB
 	select USE_OF
 	select CPU_SUPPORTS_CPUFREQ
 	select MIPS_EXTERNAL_TIMER
-- 
2.56.0

[PATCH 2/6] MIPS: Ingenic: Add and update PRIDs for XBurst II R0 and R2

[H. Nikolaus Schaller]

Add support for XBurst®1 and XBurst®2 architectures featuring the
MXU3.0 SIMD ISA, which are used in Ingenic/Lumissil MPU series.

The PRID table is updated based on Programming Manuals and hardware:
- jz4780: 0x3ee1024f (confirmed on CI20 board)
- x1000:  0x2ed1024f (unconfirmed)
- x1600:  0x00d00000 (confirmed on LX16 board)
- X1830:  0x00d00100 (unconfirmed)
- X2000:  0x00132000 (read out from LX20 board)
- X2600:  0x001320xx (confirmed 0x00132000 on LX26 board)

Additionally, clean up extra spaces in the comments for
PRID_IMP_XBURST_REV2 and PRID_IMP_XBURST2.

Note: PRID_IMP_XBURST2_R2 is imported from the vendor kernel and
is assumed to be used by the Ingenic A1 SoC family because of the
SIMD512 instruction set (MXU 3.0).

Co-developed-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
 arch/mips/include/asm/cpu.h | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 0fd9f9bbd21f1..1b88966116ffa 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -47,7 +47,7 @@
 #define PRID_COMP_CAVIUM	0x0d0000
 #define PRID_COMP_LOONGSON	0x140000
 #define PRID_COMP_INGENIC_13	0x130000	/* X2000, X2100 */
-#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4730, JZ4740, JZ4750, JZ4755, JZ4760, X1830 */
+#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4730, JZ4740, JZ4750, JZ4755, JZ4760, X1830, X1600 */
 #define PRID_COMP_INGENIC_D1	0xd10000	/* JZ4770, JZ4775, X1000 */
 #define PRID_COMP_INGENIC_E1	0xe10000	/* JZ4780 */
 
@@ -186,9 +186,11 @@
  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
  */
 
+#define PRID_IMP_XBURST		0x0000	/* XBurst®1 with ISA */
 #define PRID_IMP_XBURST_REV1	0x0200	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA	*/
-#define PRID_IMP_XBURST_REV2	0x0100	/* XBurst®1 with MXU2.0 SIMD ISA		*/
-#define PRID_IMP_XBURST2		0x2000	/* XBurst®2 with MXU2.1 SIMD ISA		*/
+#define PRID_IMP_XBURST_REV2	0x0100	/* XBurst®1 with MXU2.0 SIMD ISA */
+#define PRID_IMP_XBURST2	0x2000	/* XBurst®2 with MXU2.1 SIMD ISA */
+#define PRID_IMP_XBURST2_R2	0x2100	/* XBurst®2 with MXU3.0 SIMD ISA */
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
-- 
2.56.0

[PATCH 3/6] MIPS: Ingenic: Add cpu-probe setup for XBurst and XBurst II R2

[H. Nikolaus Schaller]

Add the missing cpu_probe_ingenic cases for PRID_IMP_XBURST and
PRID_IMP_XBURST2_R2, which are used in Ingenic/Lumissil SoCs.

This correctly initializes the CPU type, write-combine behavior,
and CPU name string ("Ingenic XBurst" and "Ingenic XBurst II R2")
based on the processor ID.

Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
 arch/mips/kernel/cpu-probe.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 489612ed9d498..f4924c14bd735 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1768,6 +1768,13 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 
 	switch (c->processor_id & PRID_IMP_MASK) {
 
+	/* XBurst®1 with ISA */
+	case PRID_IMP_XBURST:
+		c->cputype = CPU_XBURST;
+		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
+		__cpu_name[cpu] = "Ingenic XBurst";
+		break;
+
 	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
 	case PRID_IMP_XBURST_REV1:
 
@@ -1828,6 +1835,13 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 		__cpu_name[cpu] = "Ingenic XBurst II";
 		break;
 
+	/* XBurst®2 with MXU3.0 SIMD ISA */
+	case PRID_IMP_XBURST2_R2:
+		c->cputype = CPU_XBURST2;
+		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
+		__cpu_name[cpu] = "Ingenic XBurst II R2";
+		break;
+
 	default:
 		panic("Unknown Ingenic Processor ID!");
 		break;
-- 
2.56.0

[PATCH 4/6] MIPS: generic: Add MACH_INGENIC type and compatible for X1600

[H. Nikolaus Schaller]

Add support for the Ingenic/Lumissil X1600 SoC by introducing the
MACH_INGENIC_X1600 machine type.

Update the system type string mapping and add the "ingenic,x1600"
compatible string to the DT match table in the generic Ingenic board
support.

Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
 arch/mips/generic/board-ingenic.c | 3 +++
 arch/mips/include/asm/bootinfo.h  | 1 +
 2 files changed, 4 insertions(+)

diff --git a/arch/mips/generic/board-ingenic.c b/arch/mips/generic/board-ingenic.c
index 1f4906875e7bc..d6b0e2523a191 100644
--- a/arch/mips/generic/board-ingenic.c
+++ b/arch/mips/generic/board-ingenic.c
@@ -34,6 +34,8 @@ static __init char *ingenic_get_system_type(unsigned long machtype)
 		return "X2000";
 	case MACH_INGENIC_X1830:
 		return "X1830";
+	case MACH_INGENIC_X1600:
+		return "X1600";
 	case MACH_INGENIC_X1000E:
 		return "X1000E";
 	case MACH_INGENIC_X1000:
@@ -146,6 +148,7 @@ static const struct of_device_id ingenic_of_match[] __initconst = {
 	{ .compatible = "ingenic,jz4780", .data = (void *)MACH_INGENIC_JZ4780 },
 	{ .compatible = "ingenic,x1000", .data = (void *)MACH_INGENIC_X1000 },
 	{ .compatible = "ingenic,x1000e", .data = (void *)MACH_INGENIC_X1000E },
+	{ .compatible = "ingenic,x1600", .data = (void *)MACH_INGENIC_X1600 },
 	{ .compatible = "ingenic,x1830", .data = (void *)MACH_INGENIC_X1830 },
 	{ .compatible = "ingenic,x2000", .data = (void *)MACH_INGENIC_X2000 },
 	{ .compatible = "ingenic,x2000e", .data = (void *)MACH_INGENIC_X2000E },
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 2128ba9033911..2e562aa1bb198 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -81,6 +81,7 @@ enum ingenic_machine_type {
 	MACH_INGENIC_JZ4780,
 	MACH_INGENIC_X1000,
 	MACH_INGENIC_X1000E,
+	MACH_INGENIC_X1600,
 	MACH_INGENIC_X1830,
 	MACH_INGENIC_X2000,
 	MACH_INGENIC_X2000E,
-- 
2.56.0

[PATCH 5/6] MIPS: Ingenic: Expand Kconfig for X1600, X2000, and X2600 SoCs

[H. Nikolaus Schaller]

Expand MACH_INGENIC_GENERIC to select all existing and newly added
machine variants (including JZ4750/55/60/75, X1500, X1600, X2000,
X2100, and X2600).

Introduce individual Kconfig blocks for the following SoCs:
- MACH_X1600: Selects MIPS32_R2 and HIGHMEM.
- MACH_X2000 / MACH_X2600: Selects MIPS32_R5, SMP support, broadcast
  clockevents, O32 FP64 support, and weak ordering optimizations.

Also, drop the unused MIPS_CPU_SCACHE select from MACH_X1830.

In parts developed by Reimu NotMoe <reimu@sudomaker.com>

Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
 arch/mips/ingenic/Kconfig | 35 ++++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/arch/mips/ingenic/Kconfig b/arch/mips/ingenic/Kconfig
index f595b339a4b84..98da239dd6966 100644
--- a/arch/mips/ingenic/Kconfig
+++ b/arch/mips/ingenic/Kconfig
@@ -5,10 +5,19 @@ config MACH_INGENIC_GENERIC
 	select MACH_INGENIC
 	select MACH_JZ4740
 	select MACH_JZ4725B
+	select MACH_JZ4750
+	select MACH_JZ4755
+	select MACH_JZ4760
 	select MACH_JZ4770
+	select MACH_JZ4775
 	select MACH_JZ4780
 	select MACH_X1000
+	select MACH_X1500
+	select MACH_X1600
 	select MACH_X1830
+	select MACH_X2000
+	select MACH_X2100
+	select MACH_X2600
 
 choice
 	prompt "Machine type"
@@ -71,8 +80,32 @@ config MACH_X1000
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_SUPPORTS_HIGHMEM
 
+config MACH_X1600
+	bool
+	select SYS_HAS_CPU_MIPS32_R2
+	select SYS_SUPPORTS_HIGHMEM
+
 config MACH_X1830
 	bool
-	select MIPS_CPU_SCACHE
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_SUPPORTS_HIGHMEM
+
+config MACH_X2000
+	bool
+	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+	select SYS_HAS_CPU_MIPS32_R5
+	select SYS_SUPPORTS_HIGHMEM
+	select SYS_SUPPORTS_SMP
+	select MIPS_O32_FP64_SUPPORT
+	select WEAK_ORDERING
+	select WEAK_REORDERING_BEYOND_LLSC
+
+config MACH_X2600
+	bool
+	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+	select SYS_HAS_CPU_MIPS32_R5
+	select SYS_SUPPORTS_HIGHMEM
+	select SYS_SUPPORTS_SMP
+	select MIPS_O32_FP64_SUPPORT
+	select WEAK_ORDERING
+	select WEAK_REORDERING_BEYOND_LLSC
-- 
2.56.0

[PATCH 6/6] MIPS: Ingenic: Add Platform makefile for X1600 and X2000

[H. Nikolaus Schaller]

Introduce the arch/mips/ingenic/Platform file to define the default
kernel load addresses for X1600 and X2000 SoCs. Both platforms are
configured to use 0xffffffff80010000.

Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
 arch/mips/ingenic/Platform | 2 ++
 1 file changed, 2 insertions(+)
 create mode 100644 arch/mips/ingenic/Platform

diff --git a/arch/mips/ingenic/Platform b/arch/mips/ingenic/Platform
new file mode 100644
index 0000000000000..1334e8c143ce0
--- /dev/null
+++ b/arch/mips/ingenic/Platform
@@ -0,0 +1,2 @@
+load-$(CONFIG_MACH_X1600)	:= 0xffffffff80010000
+load-$(CONFIG_MACH_X2000)	:= 0xffffffff80010000
-- 
2.56.0

Re: [PATCH 1/6] MIPS: Ingenic: Fix inverted MIPS_NO_APPENDED_DTB logic in Kconfig

[Paul Cercueil]

Hi Nikolaus,

Le dimanche 25 octobre 2026 à 20:20 +0100, H. Nikolaus Schaller a
écrit :
> Correct the inverted conditional selection of BUILTIN_DTB for
> MACH_INGENIC.
> 
> Currently, the Kconfig logic forcefully selects BUILTIN_DTB when
> MIPS_NO_APPENDED_DTB is enabled (i.e., when no DTB should be appended
> to the image). This unintended behavior prevents turning off the
> built-in DTB fallback, which is required when the kernel should use
> a DTB provided directly by the bootloader.
> 
> Fix this by reversing the polarity using the logical NOT operator.
> 
> Fixes: f0f4a753079c ("MIPS: generic: Add support for Ingenic SoCs")
> Fixes: 15205fc05482 ("MIPS: ingenic: Add support for appended
> devicetree")
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>

The original code is not an 'unintended behaviour', it works as it was
designed to work: if the kernel is not configured for an appended DTB,
then a DTB should be built-in. This is because on Ingenic SoCs at
least, at the time this code was written no bootloader was passing the
DTB to the kernel.

I understand your usecase (which is very reasonnable) but this fix as-
is only fixes things for you, while breaking every other board.

I'd suggest to fix it by adding a proper description to BUILTIN_DTB (so
that it can be selected from the UI or a defconfig), then update all
arch/mips/configs/ for Ingenic based boards to enable
CONFIG_BUILTIN_DTB=y unless they rely on the appended DTB
functionality. Then this "select BUILTIN_DTB if MIPS_NO_APPENDED_DTB"
Kconfig dependency can be retired.

Cheers,
-Paul

Re: [PATCH 3/6] MIPS: Ingenic: Add cpu-probe setup for XBurst and XBurst II R2

[kernel test robot]

Hi Nikolaus,

kernel test robot noticed the following build errors:

[auto build test ERROR on linus/master]
[also build test ERROR on v7.3 next-20261023]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/H-Nikolaus-Schaller/MIPS-Ingenic-Fix-inverted-MIPS_NO_APPENDED_DTB-logic-in-Kconfig/20261025-202050
base:   linus/master
patch link:    https://lore.kernel.org/r/1658997f198411f20bc5a489e9488800e4597e19.1792956055.git.hns%40goldelico.com
patch subject: [PATCH 3/6] MIPS: Ingenic: Add cpu-probe setup for XBurst and XBurst II R2
config: mips-allnoconfig (https://download.01.org/0day-ci/archive/20261026/202610261320.3AF5hDGi-lkp@intel.com/config)
compiler: mips-linux-gcc (GCC) 16.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20261026/202610261320.3AF5hDGi-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202610261320.3AF5hDGi-lkp@intel.com/

All errors (new ones prefixed by >>):

   arch/mips/kernel/cpu-probe.c: In function 'cpu_probe_ingenic':
>> arch/mips/kernel/cpu-probe.c:1840:30: error: 'CPU_XBURST2' undeclared (first use in this function); did you mean 'CPU_XBURST'?
    1840 |                 c->cputype = CPU_XBURST2;
         |                              ^~~~~~~~~~~
         |                              CPU_XBURST
   arch/mips/kernel/cpu-probe.c:1840:30: note: each undeclared identifier is reported only once for each function it appears in


vim +1840 arch/mips/kernel/cpu-probe.c

  1751	
  1752	static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
  1753	{
  1754		decode_configs(c);
  1755	
  1756		/*
  1757		 * XBurst misses a config2 register, so config3 decode was skipped in
  1758		 * decode_configs().
  1759		 */
  1760		decode_config3(c);
  1761	
  1762		/* XBurst does not implement the CP0 counter. */
  1763		c->options &= ~MIPS_CPU_COUNTER;
  1764		BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter);
  1765	
  1766		/* XBurst has virtually tagged icache */
  1767		c->icache.flags |= MIPS_CACHE_VTAG;
  1768	
  1769		switch (c->processor_id & PRID_IMP_MASK) {
  1770	
  1771		/* XBurst®1 with ISA */
  1772		case PRID_IMP_XBURST:
  1773			c->cputype = CPU_XBURST;
  1774			c->writecombine = _CACHE_UNCACHED_ACCELERATED;
  1775			__cpu_name[cpu] = "Ingenic XBurst";
  1776			break;
  1777	
  1778		/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
  1779		case PRID_IMP_XBURST_REV1:
  1780	
  1781			/*
  1782			 * The XBurst core by default attempts to avoid branch target
  1783			 * buffer lookups by detecting & special casing loops. This
  1784			 * feature will cause BogoMIPS and lpj calculate in error.
  1785			 * Set cp0 config7 bit 4 to disable this feature.
  1786			 */
  1787			set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
  1788	
  1789			switch (c->processor_id & PRID_COMP_MASK) {
  1790	
  1791			/*
  1792			 * The config0 register in the XBurst CPUs with a processor ID of
  1793			 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
  1794			 * but they don't actually support this ISA.
  1795			 */
  1796			case PRID_COMP_INGENIC_D0:
  1797				c->isa_level &= ~MIPS_CPU_ISA_M32R2;
  1798	
  1799				/* FPU is not properly detected on JZ4760(B). */
  1800				if (c->processor_id == 0x2ed0024f)
  1801					c->options |= MIPS_CPU_FPU;
  1802	
  1803				fallthrough;
  1804	
  1805			/*
  1806			 * The config0 register in the XBurst CPUs with a processor ID of
  1807			 * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned
  1808			 * huge page tlb mode, this mode is not compatible with the MIPS
  1809			 * standard, it will cause tlbmiss and into an infinite loop
  1810			 * (line 21 in the tlb-funcs.S) when starting the init process.
  1811			 * After chip reset, the default is HPTLB mode, Write 0xa9000000
  1812			 * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent
  1813			 * getting stuck.
  1814			 */
  1815			case PRID_COMP_INGENIC_D1:
  1816				write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
  1817				break;
  1818	
  1819			default:
  1820				break;
  1821			}
  1822			fallthrough;
  1823	
  1824		/* XBurst®1 with MXU2.0 SIMD ISA */
  1825		case PRID_IMP_XBURST_REV2:
  1826			/* Ingenic uses the WA bit to achieve write-combine memory writes */
  1827			c->writecombine = _CACHE_CACHABLE_WA;
  1828			c->cputype = CPU_XBURST;
  1829			__cpu_name[cpu] = "Ingenic XBurst";
  1830			break;
  1831	
  1832		/* XBurst®2 with MXU2.1 SIMD ISA */
  1833		case PRID_IMP_XBURST2:
  1834			c->cputype = CPU_XBURST;
  1835			__cpu_name[cpu] = "Ingenic XBurst II";
  1836			break;
  1837	
  1838		/* XBurst®2 with MXU3.0 SIMD ISA */
  1839		case PRID_IMP_XBURST2_R2:
> 1840			c->cputype = CPU_XBURST2;
  1841			c->writecombine = _CACHE_UNCACHED_ACCELERATED;
  1842			__cpu_name[cpu] = "Ingenic XBurst II R2";
  1843			break;
  1844	
  1845		default:
  1846			panic("Unknown Ingenic Processor ID!");
  1847			break;
  1848		}
  1849	}
  1850	

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 3/6] MIPS: Ingenic: Add cpu-probe setup for XBurst and XBurst II R2

[kernel test robot]

Hi Nikolaus,

kernel test robot noticed the following build errors:

[auto build test ERROR on linus/master]
[also build test ERROR on v7.3 next-20261023]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/H-Nikolaus-Schaller/MIPS-Ingenic-Fix-inverted-MIPS_NO_APPENDED_DTB-logic-in-Kconfig/20261025-202050
base:   linus/master
patch link:    https://lore.kernel.org/r/1658997f198411f20bc5a489e9488800e4597e19.1792956055.git.hns%40goldelico.com
patch subject: [PATCH 3/6] MIPS: Ingenic: Add cpu-probe setup for XBurst and XBurst II R2
config: mips-bcm47xx_defconfig (https://download.01.org/0day-ci/archive/20261026/202610262006.fTqK3Ge7-lkp@intel.com/config)
compiler: clang version 24.0.0git (https://github.com/llvm/llvm-project 186e70f4e6a1521991d2340d3d49b23b1beff11f)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20261026/202610262006.fTqK3Ge7-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202610262006.fTqK3Ge7-lkp@intel.com/

All errors (new ones prefixed by >>):

>> arch/mips/kernel/cpu-probe.c:1840:16: error: use of undeclared identifier 'CPU_XBURST2'; did you mean 'CPU_XBURST'?
    1840 |                 c->cputype = CPU_XBURST2;
         |                              ^~~~~~~~~~~
         |                              CPU_XBURST
   arch/mips/include/asm/cpu.h:317:32: note: 'CPU_XBURST' declared here
     317 |         CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON32, CPU_M14KC,
         |                                       ^
   1 error generated.


vim +1840 arch/mips/kernel/cpu-probe.c

  1751	
  1752	static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
  1753	{
  1754		decode_configs(c);
  1755	
  1756		/*
  1757		 * XBurst misses a config2 register, so config3 decode was skipped in
  1758		 * decode_configs().
  1759		 */
  1760		decode_config3(c);
  1761	
  1762		/* XBurst does not implement the CP0 counter. */
  1763		c->options &= ~MIPS_CPU_COUNTER;
  1764		BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter);
  1765	
  1766		/* XBurst has virtually tagged icache */
  1767		c->icache.flags |= MIPS_CACHE_VTAG;
  1768	
  1769		switch (c->processor_id & PRID_IMP_MASK) {
  1770	
  1771		/* XBurst®1 with ISA */
  1772		case PRID_IMP_XBURST:
  1773			c->cputype = CPU_XBURST;
  1774			c->writecombine = _CACHE_UNCACHED_ACCELERATED;
  1775			__cpu_name[cpu] = "Ingenic XBurst";
  1776			break;
  1777	
  1778		/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
  1779		case PRID_IMP_XBURST_REV1:
  1780	
  1781			/*
  1782			 * The XBurst core by default attempts to avoid branch target
  1783			 * buffer lookups by detecting & special casing loops. This
  1784			 * feature will cause BogoMIPS and lpj calculate in error.
  1785			 * Set cp0 config7 bit 4 to disable this feature.
  1786			 */
  1787			set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
  1788	
  1789			switch (c->processor_id & PRID_COMP_MASK) {
  1790	
  1791			/*
  1792			 * The config0 register in the XBurst CPUs with a processor ID of
  1793			 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
  1794			 * but they don't actually support this ISA.
  1795			 */
  1796			case PRID_COMP_INGENIC_D0:
  1797				c->isa_level &= ~MIPS_CPU_ISA_M32R2;
  1798	
  1799				/* FPU is not properly detected on JZ4760(B). */
  1800				if (c->processor_id == 0x2ed0024f)
  1801					c->options |= MIPS_CPU_FPU;
  1802	
  1803				fallthrough;
  1804	
  1805			/*
  1806			 * The config0 register in the XBurst CPUs with a processor ID of
  1807			 * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned
  1808			 * huge page tlb mode, this mode is not compatible with the MIPS
  1809			 * standard, it will cause tlbmiss and into an infinite loop
  1810			 * (line 21 in the tlb-funcs.S) when starting the init process.
  1811			 * After chip reset, the default is HPTLB mode, Write 0xa9000000
  1812			 * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent
  1813			 * getting stuck.
  1814			 */
  1815			case PRID_COMP_INGENIC_D1:
  1816				write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
  1817				break;
  1818	
  1819			default:
  1820				break;
  1821			}
  1822			fallthrough;
  1823	
  1824		/* XBurst®1 with MXU2.0 SIMD ISA */
  1825		case PRID_IMP_XBURST_REV2:
  1826			/* Ingenic uses the WA bit to achieve write-combine memory writes */
  1827			c->writecombine = _CACHE_CACHABLE_WA;
  1828			c->cputype = CPU_XBURST;
  1829			__cpu_name[cpu] = "Ingenic XBurst";
  1830			break;
  1831	
  1832		/* XBurst®2 with MXU2.1 SIMD ISA */
  1833		case PRID_IMP_XBURST2:
  1834			c->cputype = CPU_XBURST;
  1835			__cpu_name[cpu] = "Ingenic XBurst II";
  1836			break;
  1837	
  1838		/* XBurst®2 with MXU3.0 SIMD ISA */
  1839		case PRID_IMP_XBURST2_R2:
> 1840			c->cputype = CPU_XBURST2;
  1841			c->writecombine = _CACHE_UNCACHED_ACCELERATED;
  1842			__cpu_name[cpu] = "Ingenic XBurst II R2";
  1843			break;
  1844	
  1845		default:
  1846			panic("Unknown Ingenic Processor ID!");
  1847			break;
  1848		}
  1849	}
  1850	

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 1/6] MIPS: Ingenic: Fix inverted MIPS_NO_APPENDED_DTB logic in Kconfig

[H. Nikolaus Schaller]

Hi Paul,

> Am 26.10.2026 um 00:41 schrieb Paul Cercueil <paul@crapouillou.net>:
> 
> The original code is not an 'unintended behaviour', it works as it was
> designed to work: if the kernel is not configured for an appended DTB,
> then a DTB should be built-in. This is because on Ingenic SoCs at
> least, at the time this code was written no bootloader was passing the
> DTB to the kernel.
> 
> I understand your usecase (which is very reasonnable) but this fix as-
> is only fixes things for you, while breaking every other board.
> 
> I'd suggest to fix it by adding a proper description to BUILTIN_DTB (so
> that it can be selected from the UI or a defconfig), then update all
> arch/mips/configs/ for Ingenic based boards to enable
> CONFIG_BUILTIN_DTB=y unless they rely on the appended DTB
> functionality. Then this "select BUILTIN_DTB if MIPS_NO_APPENDED_DTB"
> Kconfig dependency can be retired.

Thank you for the detailed feedback and for explaining the historical
background. That makes perfect sense.

I will follow your suggestion and add split this in a V2 patch series so that:
- Adds a proper prompt/description to BUILTIN_DTB so it becomes user-selectable
- Update the existing Ingenic defconfigs to explicitly enable CONFIG_BUILTIN_DTB=y
  where needed (I think there are just 4 cases)
- Remove the automatic select BUILTIN_DTB if MIPS_NO_APPENDED_DTB from MACH_INGENIC.

This should cleanly support my (and likely other's) use case of a
bootloader-provided DTB without breaking any existing board.

BTW: we have this working with U-Boot on CI20 as well. So a generic ingenic
kernel and all board specific cases in the DTB.

I'll update and also consider the feedback from Sashiko-bot and others for
the other patches in this series.

BR and thanks,
Nikolaus