[PATCH 10/17] platform/x86/intel/ifs: Validate TID_BIT_SHIFT matches topology_cluster_cpumask()

[Ehab Ababneh <ehab.ababneh@intel.com>]

From: Qiuxu Zhuo <qiuxu.zhuo@intel.com>

The intel_ifs driver assumes logical processors indicated by TID_BIT_SHIFT
[1] that share the same SCAN test engine match topology_cluster_cpumask().
Validate this assumption during driver initialization and fail loading if
it doesn't hold.

[1] Vol. 4 "Table 2-56. Additional MSRs Supported by the Intel® Xeon®
    6 P-Core Processors" in the Intel Software Developers' Manual,
    March 2025.

Suggested-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Ehab Ababneh <ehab.ababneh@intel.com>
---
 arch/x86/include/asm/msr-index.h      |  1 +
 drivers/platform/x86/intel/ifs/core.c | 48 +++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 554ce662fdf4..e93c76389ca5 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -281,6 +281,7 @@
 #define MSR_INTEGRITY_CAPS_PERIODIC_SCAN_BIST_BIT	4
 #define MSR_INTEGRITY_CAPS_PERIODIC_SCAN_BIST		BIT(MSR_INTEGRITY_CAPS_PERIODIC_SCAN_BIST_BIT)
 #define MSR_INTEGRITY_CAPS_SAF_GEN_MASK			GENMASK_ULL(10, 9)
+#define MSR_INTEGRITY_CAPS_TID_BIT_SHIFT_MASK		GENMASK_ULL(20, 16)
 #define MSR_INTEGRITY_CAPS_ALL_LP_JOIN_BIT		21
 #define MSR_INTEGRITY_CAPS_ALL_LP_JOIN			BIT(MSR_INTEGRITY_CAPS_ALL_LP_JOIN_BIT)
 
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index f2d2caab0479..c830a02fe7b3 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /* Copyright(c) 2022 Intel Corporation. */
 
+#define pr_fmt(fmt)  "intel_ifs: " fmt
+
 #include <linux/bitfield.h>
 #include <linux/module.h>
 #include <linux/kdev_t.h>
@@ -69,6 +71,45 @@ static struct ifs_device ifs_devices[] = {
 	},
 };
 
+/*
+ * Test whether logical processors indicated by TID_BIT_SHIFT that share the
+ * same SCAN test engine match the cpumask from topology_cluster_cpumask().
+ */
+static bool topology_cluster_matched(u32 msrval)
+{
+	u32 dist, shift = FIELD_GET(MSR_INTEGRITY_CAPS_TID_BIT_SHIFT_MASK, msrval);
+	const cpumask_t *cpumask = topology_cluster_cpumask(0);
+	u32 delta, step = 0, first = cpu_data(0).topo.apicid;
+	unsigned int cpu, cpus;
+
+	/* Get the minimal APIC ID step among the CPUs in the same cluster. */
+	for_each_cpu_andnot(cpu, cpumask, cpumask_of(0)) {
+		delta = abs(cpu_data(cpu).topo.apicid - first);
+
+		if (!step) {
+			step = delta;
+			continue;
+		}
+
+		if (step > delta)
+			step = delta;
+	}
+
+	/* A Hyper-Threading (HT) system with HT disabled. */
+	if (!step)
+		step = 2;
+
+	cpus = cpumask_weight(cpumask);
+	dist = step * cpus;
+
+	if (dist != (1 << shift)) {
+		pr_err_once("APICID step %u, group cpus %u, TID_BIT_SHIFT %u\n", step, cpus, shift);
+		return false;
+	}
+
+	return true;
+}
+
 #define IFS_NUMTESTS ARRAY_SIZE(ifs_devices)
 
 static void ifs_cleanup(void)
@@ -122,6 +163,13 @@ static int __init ifs_init(void)
 		 */
 		ifs_devices[i].rw_data.all_lp_join = ifs_devices[i].rw_data.generation ?
 						(msrval & MSR_INTEGRITY_CAPS_ALL_LP_JOIN) : true;
+
+		if (ifs_devices[i].rw_data.all_lp_join && !topology_cluster_matched(msrval)) {
+			pr_err_once("TID_BIT_SHIFT mismatched topology_cluster_cpumask().\n");
+			ret = -EINVAL;
+			goto err_exit;
+		}
+
 		ifs_devices[i].rw_data.array_gen = (u32)m->driver_data;
 		ret = misc_register(&ifs_devices[i].misc);
 		if (ret)
-- 
2.43.0