From: Ehab Ababneh <ehab.ababneh@intel.com>
To: ilpo.jarvinen@linux.intel.com, hansg@kernel.org, tony.luck@intel.com
Cc: ashok.raj.linux@gmail.com, platform-driver-x86@vger.kernel.org,
linux-kernel@vger.kernel.org, tglx@kernel.org, mingo@redhat.com,
bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org,
hpa@zytor.com, rostedt@goodmis.org, mhiramat@kernel.org,
mathieu.desnoyers@efficios.com,
linux-trace-kernel@vger.kernel.org, peterz@infradead.org,
sathyanarayanan.kuppuswamy@linux.intel.com, pengfei.xu@intel.com,
ravi.v.shankar@intel.com
Subject: [PATCH 08/17] platform/x86/intel/ifs: Enumerate the bit to determine if CPUs need to join for IFS tests
Date: Mon, 26 Oct 2026 11:38:11 -0700 [thread overview]
Message-ID: <20261026183820.129459-9-ehab.ababneh@intel.com> (raw)
In-Reply-To: <20261026183820.129459-1-ehab.ababneh@intel.com>
From: Jithu Joseph <jithu.joseph@intel.com>
Starting with Granite Rapids (GNR), bit 21 (ALL_LP_JOIN_NEEDED) of
MSR_INTEGRITY_CAPABILITIES register [1] indicates whether all CPUs sharing
the scan test engine need to be tested together. These CPUs must join
using MSR_ACTIVATE_SCAN.
Add an enumeration of bit 21 to determine if CPUs need to join to run IFS
tests together.
[1] Vol. 4 "Table 2-56. Additional MSRs Supported by the Intel® Xeon®
6 P-Core Processors" in the Intel Software Developers' Manual,
March 2025.
[ Qiuxu: Elaborate commit message. ]
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Signed-off-by: Ehab Ababneh <ehab.ababneh@intel.com>
---
arch/x86/include/asm/msr-index.h | 2 ++
drivers/platform/x86/intel/ifs/core.c | 12 ++++++++++++
drivers/platform/x86/intel/ifs/ifs.h | 2 ++
3 files changed, 16 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 660b0c332be2..554ce662fdf4 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -281,6 +281,8 @@
#define MSR_INTEGRITY_CAPS_PERIODIC_SCAN_BIST_BIT 4
#define MSR_INTEGRITY_CAPS_PERIODIC_SCAN_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_SCAN_BIST_BIT)
#define MSR_INTEGRITY_CAPS_SAF_GEN_MASK GENMASK_ULL(10, 9)
+#define MSR_INTEGRITY_CAPS_ALL_LP_JOIN_BIT 21
+#define MSR_INTEGRITY_CAPS_ALL_LP_JOIN BIT(MSR_INTEGRITY_CAPS_ALL_LP_JOIN_BIT)
#define MSR_LBR_NHM_FROM 0x00000680
#define MSR_LBR_NHM_TO 0x000006c0
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index 85a04ecc9dbe..f2d2caab0479 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -110,6 +110,18 @@ static int __init ifs_init(void)
continue;
ifs_devices[i].rw_data.generation = FIELD_GET(MSR_INTEGRITY_CAPS_SAF_GEN_MASK,
msrval);
+ /*
+ * For Sapphire Rapids and Emerald Rapids (SAF_GEN=0), the ALL_LP_JOIN
+ * indicator is unavailable. However, all the threads within a core still
+ * need to run IFS simultaneously, so the variable 'all_lp_join' is
+ * forced to true.
+ *
+ * For Granite Rapids and later generations (SAF_GEN=2), the ALL_LP_JOIN
+ * indicator is available, the variable 'all_lp_join' is determined by
+ * this indicator.
+ */
+ ifs_devices[i].rw_data.all_lp_join = ifs_devices[i].rw_data.generation ?
+ (msrval & MSR_INTEGRITY_CAPS_ALL_LP_JOIN) : true;
ifs_devices[i].rw_data.array_gen = (u32)m->driver_data;
ret = misc_register(&ifs_devices[i].misc);
if (ret)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index f52287745366..814ebac10a5d 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -295,6 +295,7 @@ struct ifs_test_msrs {
* @generation: IFS test generation enumerated by hardware
* @chunk_size: size of a test chunk
* @array_gen: test generation of array test
+ * @all_lp_join: all logical processors join test
*/
struct ifs_data {
int loaded_version;
@@ -307,6 +308,7 @@ struct ifs_data {
u32 generation;
u32 chunk_size;
u32 array_gen;
+ bool all_lp_join;
};
struct ifs_work {
--
2.43.0
next prev parent reply other threads:[~2026-10-26 18:35 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-26 18:38 [PATCH 00/17] platform/x86/intel/ifs: Support group-based In-Field Scan and Diamond Rapids Ehab Ababneh
2026-10-26 18:38 ` [PATCH 01/17] platform/x86/intel/ifs: Revert SBAF feature Ehab Ababneh
2026-10-26 18:38 ` [PATCH 02/17] platform/x86/intel/ifs: Fix IFS sysfs interfaces in the comments Ehab Ababneh
2026-10-26 18:38 ` [PATCH 03/17] platform/x86/intel/ifs: Clarify In-Field Scan MSR bit macro definitions Ehab Ababneh
2026-10-26 18:38 ` [PATCH 04/17] platform/x86/intel/ifs: Use u64 to define the bits of IFS MSR registers Ehab Ababneh
2026-10-26 18:38 ` [PATCH 05/17] platform/x86/intel/ifs: Early return on the IFS image hash/chunk error Ehab Ababneh
2026-10-26 18:38 ` [PATCH 06/17] platform/x86/intel/ifs: Refactor Array BIST function interface Ehab Ababneh
2026-10-26 18:38 ` [PATCH 07/17] stop_machine: Add stop_cluster_cpuslocked() for per-cluster operations Ehab Ababneh
2026-10-26 18:38 ` Ehab Ababneh [this message]
2026-10-26 18:38 ` [PATCH 09/17] platform/x86/intel/ifs: Select CPUs from topology_cluster_cpumask() for simultaneous IFS tests Ehab Ababneh
2026-10-26 18:38 ` [PATCH 10/17] platform/x86/intel/ifs: Validate TID_BIT_SHIFT matches topology_cluster_cpumask() Ehab Ababneh
2026-10-26 18:38 ` [PATCH 11/17] platform/x86/intel/ifs: Track and report scan results on a per-CPU basis Ehab Ababneh
2026-10-26 18:38 ` [PATCH 12/17] platform/x86/intel/ifs: Add new sysfs interfaces {status, details, cpus_ran}_list Ehab Ababneh
2026-10-26 18:38 ` [PATCH 13/17] platform/x86/intel/ifs: Add additional details sysfs interface Ehab Ababneh
2026-10-26 18:38 ` [PATCH 14/17] platform/x86/intel/ifs: Add Intel Diamond Rapids server support Ehab Ababneh
2026-10-26 18:38 ` [PATCH 15/17] platform/x86/intel/ifs: Remove limit on number of batch files Ehab Ababneh
2026-10-26 18:38 ` [PATCH 16/17] platform/x86/intel/ifs: Update IFS documentation Ehab Ababneh
2026-10-26 18:38 ` [PATCH 17/17] Documentation/ABI: Update IFS ABI doc Ehab Ababneh
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261026183820.129459-9-ehab.ababneh@intel.com \
--to=ehab.ababneh@intel.com \
--cc=ashok.raj.linux@gmail.com \
--cc=bp@alien8.de \
--cc=dave.hansen@linux.intel.com \
--cc=hansg@kernel.org \
--cc=hpa@zytor.com \
--cc=ilpo.jarvinen@linux.intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-trace-kernel@vger.kernel.org \
--cc=mathieu.desnoyers@efficios.com \
--cc=mhiramat@kernel.org \
--cc=mingo@redhat.com \
--cc=pengfei.xu@intel.com \
--cc=peterz@infradead.org \
--cc=platform-driver-x86@vger.kernel.org \
--cc=ravi.v.shankar@intel.com \
--cc=rostedt@goodmis.org \
--cc=sathyanarayanan.kuppuswamy@linux.intel.com \
--cc=tglx@kernel.org \
--cc=tony.luck@intel.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®