Re: [PATCH v2 05/14] perf cs-etm: Use the recorded instruction size for A32 and A64

[Leo Yan <leo.yan@arm.com>]

On Tue, Sep 29, 2026 at 02:55:28PM +0100, James Clark wrote:
> 
> 
> On 23/09/2026 16:21, Leo Yan wrote:
> > Use packet->last_instr_size in cs_etm__instr_size() instead of a
> > hard-coded value, allowing the decoder to supply the instruction size.
> > 
> > Keep per-address decoding for T32. A range can mix 16-bit and 32-bit
> > instructions, so last_instr_size describes only the final instruction
> > and cannot determine the size at an arbitrary address in the range.
> > 
> > Assisted-by: Codex:gpt-6
> > Signed-off-by: Leo Yan <leo.yan@arm.com>
> > ---
> >   tools/perf/util/cs-etm.c | 3 +--
> >   1 file changed, 1 insertion(+), 2 deletions(-)
> > 
> > diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
> > index 2d1ab34f7b6b5a6331005c16c6a418d123c815eb..0163d93ac2d537a2190536e77d24628b4d707751 100644
> > --- a/tools/perf/util/cs-etm.c
> > +++ b/tools/perf/util/cs-etm.c
> > @@ -1358,8 +1358,7 @@ static inline int cs_etm__instr_size(struct cs_etm_queue *etmq,
> >   	if (packet->isa == CS_ETM_ISA_T32)
> >   		return cs_etm__t32_instr_size(etmq, tidq, packet, addr);
> > -	/* Otherwise, 4-byte instruction size for A32/A64 */
> > -	return 4;
> > +	return packet->last_instr_size;
> 
> Why not use last_instr_size for CS_ETM_ISA_T32 too?

T32 needs per-address decoding because a range can mix 2-byte and
4-byte instructions.

> I'm wondering how and when this change actually makes a difference?
> last_instr_size isn't any better than '4' for any instruction in the
> range other than the last one, so it's not clear what the issue is.

It prepares for the later patch that synthesizes exception entries
separately, where an exception packet can carry last_instr_size = 0.
Preserving that zero avoids advancing the reconstructed return address
by four bytes.

I will update the commit message for this.

Thanks,
Leo