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From: Joseph Telaak via B4 Relay <devnull+joseph.telaak.dev@kernel.org>
To: Linus Walleij <linusw@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	Bartosz Golaszewski <brgl@kernel.org>
Cc: Chuanhong Guo <gch981213@gmail.com>,
	linux-gpio@vger.kernel.org,  devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,  Joseph Telaak <joseph@telaak.dev>
Subject: [PATCH 1/2] dt-bindings: pinctrl: Add Siflower SF19A2890 pin controller
Date: Wed, 04 Nov 2026 02:21:17 -0500	[thread overview]
Message-ID: <20261104-sf19a2890-pinctrl-v1-1-4bb83afdbacf@telaak.dev> (raw)
In-Reply-To: <20261104-sf19a2890-pinctrl-v1-0-4bb83afdbacf@telaak.dev>

From: Joseph Telaak <joseph@telaak.dev>

The pin controller of the Siflower SF19A2890 selects the function of
each of its 49 pins and sets their bias, input enable, Schmitt trigger
and drive strength. Each pin has a register pair of its own, and each
pin state node holds subnodes that set some of its pins.

Signed-off-by: Joseph Telaak <joseph@telaak.dev>
---
 .../pinctrl/siflower,sf19a2890-pinctrl.yaml        | 113 +++++++++++++++++++++
 1 file changed, 113 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/siflower,sf19a2890-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/siflower,sf19a2890-pinctrl.yaml
new file mode 100644
index 000000000..8b52d3175
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/siflower,sf19a2890-pinctrl.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/siflower,sf19a2890-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Siflower SF19A2890 pin controller
+
+maintainers:
+  - Joseph Telaak <joseph@telaak.dev>
+
+description:
+  The pin controller of the Siflower SF19A2890 selects the function of
+  each of its 49 pins and sets their bias, input enable, Schmitt trigger
+  and drive strength. The GPIO function is selected through the GPIO
+  controller, which maps its lines onto these pins with gpio-ranges.
+
+properties:
+  compatible:
+    const: siflower,sf19a2890-pinctrl
+
+  reg:
+    maxItems: 1
+
+patternProperties:
+  '-pins$':
+    type: object
+    description:
+      A pin state. Each subnode sets the function and configuration of
+      some of its pins.
+
+    patternProperties:
+      '^pins(-[a-z0-9]+)*$':
+        type: object
+        $ref: /schemas/pinctrl/pincfg-node.yaml#
+        allOf:
+          - $ref: /schemas/pinctrl/pinmux-node.yaml#
+
+        properties:
+          pins:
+            items:
+              enum: [JTAG_TDO, JTAG_TDI, JTAG_TMS, JTAG_TCK, JTAG_RST,
+                     SPI_TXD, SPI_RXD, SPI_CLK, SPI_CSN, UART_TX, UART_RX,
+                     I2C_DAT, I2C_CLK, RGMII_GTX_CLK, RGMII_TXCLK,
+                     RGMII_TXD0, RGMII_TXD1, RGMII_TXD2, RGMII_TXD3,
+                     RGMII_TXCTL, RGMII_RXCLK, RGMII_RXD0, RGMII_RXD1,
+                     RGMII_RXD2, RGMII_RXD3, RGMII_RXCTL, RGMII_COL,
+                     RGMII_CRS, RGMII_MDC, RGMII_MDIO, HB0_PA_EN,
+                     HB0_LNA_EN, HB0_SW_CTRL0, HB0_SW_CTRL1, HB1_PA_EN,
+                     HB1_LNA_EN, HB1_SW_CTRL0, HB1_SW_CTRL1, LB0_PA_EN,
+                     LB0_LNA_EN, LB0_SW_CTRL0, LB0_SW_CTRL1, LB1_PA_EN,
+                     LB1_LNA_EN, LB1_SW_CTRL0, LB1_SW_CTRL1, CLK_OUT,
+                     EXT_CLK_IN, DRVVBUS0]
+            minItems: 1
+            maxItems: 49
+
+          function:
+            enum: [i2c0, jtag, mdio, pwm0, pwm1, rgmii, spi, uart0, uart1,
+                   uart2, wlan]
+
+          bias-disable: true
+
+          bias-pull-up: true
+
+          bias-pull-down: true
+
+          input-enable: true
+
+          input-schmitt-enable: true
+
+          input-schmitt-disable: true
+
+          drive-strength:
+            description: Output drive strength in mA.
+            enum: [6, 9, 12, 15, 18, 21, 24, 27]
+
+        required:
+          - pins
+
+        additionalProperties: false
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - $ref: pinctrl.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    pinctrl@19e3fc00 {
+        compatible = "siflower,sf19a2890-pinctrl";
+        reg = <0x19e3fc00 0x400>;
+
+        uart0-pins {
+            pins-tx {
+                pins = "UART_TX";
+                function = "uart0";
+                bias-pull-up;
+            };
+
+            pins-rx {
+                pins = "UART_RX";
+                function = "uart0";
+                input-enable;
+                bias-pull-up;
+            };
+        };
+    };

-- 
Git-155)



  reply	other threads:[~2026-11-04  7:21 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-04  7:21 [PATCH 0/2] pinctrl: Add the " Joseph Telaak via B4 Relay
2026-11-04  7:21 ` Joseph Telaak via B4 Relay [this message]
2026-11-04 23:49   ` [PATCH 1/2] dt-bindings: pinctrl: Add " Conor Dooley
2026-11-05  0:45     ` Joseph Telaak
2026-11-04  7:21 ` [PATCH 2/2] pinctrl: Add Siflower SF19A2890 pin controller driver Joseph Telaak via B4 Relay
2026-11-04 23:54   ` Conor Dooley
2026-11-05  0:54     ` Joseph Telaak
2026-11-05  1:35       ` Conor Dooley

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