From: Sumit Gupta <sumitg@nvidia.com>
To: <rafael@kernel.org>, <viresh.kumar@linaro.org>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <treding@nvidia.com>,
<jonathanh@nvidia.com>, <linux-pm@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>
Cc: <bbasu@nvidia.com>, <sumitg@nvidia.com>
Subject: [PATCH 9/9] arm64: tegra: Add CCPLEX cluster node for Tegra264
Date: Wed, 4 Nov 2026 23:45:21 +0530 [thread overview]
Message-ID: <20261104181521.3003578-10-sumitg@nvidia.com> (raw)
In-Reply-To: <20261104181521.3003578-1-sumitg@nvidia.com>
Add the CCPLEX cluster node under bus@8100000000. The cpufreq driver
uses it to request CPU frequencies.
Add the generic "performance-domains" property to each CPU, referencing
this node. The driver uses the domain index to group CPUs that share a
cluster-clock unit and to select their core_freq_req register. Each
cluster has one CPU, and two clusters share a unit, so each domain
holds two CPUs.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 5ab34cd09a3d..10ea51802e8c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3964,6 +3964,13 @@ i2c12: i2c@c6d0000 {
status = "disabled";
};
+ ccplex: ccplex@30000000 {
+ compatible = "nvidia,tegra264-ccplex-cluster";
+ reg = <0x00 0x30000000 0x0 0x00cf0000>;
+ #performance-domain-cells = <1>;
+ nvidia,bpmp = <&bpmp>;
+ };
+
gic: interrupt-controller@46000000 {
compatible = "arm,gic-v3";
reg = <0x00 0x46000000 0x0 0x010000>, /* GICD */
@@ -4384,6 +4391,7 @@ cpu0: cpu@0 {
reg = <0x00000>;
enable-method = "psci";
+ performance-domains = <&ccplex 0>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4400,6 +4408,7 @@ cpu1: cpu@10000 {
reg = <0x10000>;
enable-method = "psci";
+ performance-domains = <&ccplex 0>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4416,6 +4425,7 @@ cpu2: cpu@20000 {
reg = <0x20000>;
enable-method = "psci";
+ performance-domains = <&ccplex 1>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4432,6 +4442,7 @@ cpu3: cpu@30000 {
reg = <0x30000>;
enable-method = "psci";
+ performance-domains = <&ccplex 1>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4448,6 +4459,7 @@ cpu4: cpu@40000 {
reg = <0x40000>;
enable-method = "psci";
+ performance-domains = <&ccplex 2>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4464,6 +4476,7 @@ cpu5: cpu@50000 {
reg = <0x50000>;
enable-method = "psci";
+ performance-domains = <&ccplex 2>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4480,6 +4493,7 @@ cpu6: cpu@60000 {
reg = <0x60000>;
enable-method = "psci";
+ performance-domains = <&ccplex 3>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4496,6 +4510,7 @@ cpu7: cpu@70000 {
reg = <0x70000>;
enable-method = "psci";
+ performance-domains = <&ccplex 3>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4512,6 +4527,7 @@ cpu8: cpu@80000 {
reg = <0x80000>;
enable-method = "psci";
+ performance-domains = <&ccplex 4>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4528,6 +4544,7 @@ cpu9: cpu@90000 {
reg = <0x90000>;
enable-method = "psci";
+ performance-domains = <&ccplex 4>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4544,6 +4561,7 @@ cpu10: cpu@a0000 {
reg = <0xa0000>;
enable-method = "psci";
+ performance-domains = <&ccplex 5>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4560,6 +4578,7 @@ cpu11: cpu@b0000 {
reg = <0xb0000>;
enable-method = "psci";
+ performance-domains = <&ccplex 5>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4576,6 +4595,7 @@ cpu12: cpu@c0000 {
reg = <0xc0000>;
enable-method = "psci";
+ performance-domains = <&ccplex 6>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -4592,6 +4612,7 @@ cpu13: cpu@d0000 {
reg = <0xd0000>;
enable-method = "psci";
+ performance-domains = <&ccplex 6>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
--
2.34.1
prev parent reply other threads:[~2026-11-04 18:16 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-04 18:15 [PATCH 0/9] cpufreq: tegra194: add Tegra264 support Sumit Gupta
2026-11-04 18:15 ` [PATCH 1/9] cpufreq: tegra194: move MPIDR read to CPU hotplug callback Sumit Gupta
2026-11-04 18:15 ` [PATCH 2/9] cpufreq: tegra194: remove duplicate counter sampling loops Sumit Gupta
2026-11-04 18:15 ` [PATCH 3/9] cpufreq: tegra194: add tegra_counter_delta helper Sumit Gupta
2026-11-04 18:15 ` [PATCH 4/9] cpufreq: tegra194: add per-SoC counter mask Sumit Gupta
2026-11-04 18:15 ` [PATCH 5/9] cpufreq: tegra194: split MMIO mapping from ACTMON offset Sumit Gupta
2026-11-04 18:15 ` [PATCH 6/9] dt-bindings: arm: nvidia: Document the Tegra264 CCPLEX cluster Sumit Gupta
2026-11-04 18:15 ` [PATCH 7/9] cpufreq: tegra194: derive frequency domain from device tree Sumit Gupta
2026-11-04 18:15 ` [PATCH 8/9] cpufreq: tegra194: Add support for Tegra264 Sumit Gupta
2026-11-04 18:15 ` Sumit Gupta [this message]
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