Re: [PATCH 00/25] riscv: add support for the Metanoia MT2824 SoC and MT5824 EVB

[Conor Dooley <conor@kernel.org>]

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On Fri, Nov 06, 2026 at 10:29:57AM +0100, Benoît Monin wrote:
> Hi all,
> 
> This series adds initial upstream support for the Metanoia MT2824 SoC
> and its MT5824 evaluation board.
> 
> The MT2824 is a dual-core RISC-V SoC built on Andes AX45MP cores. It
> integrates two 8250-compatible UARTs, the Andes PLIC/PLICSW/PLMT interrupt
> and timer blocks, the AX45MP L2 cache controller, a simple reset controller
> and a system reboot controller, the ATCWDT200 watchdog, one QSPI and eight
> ATCSPI200 SPI controllers, a Synopsys DWC MSHC 2.00a eMMC/SD controller,
> and a Synopsys DWC2 USB2 host controller with a reset-only USB2 PHY.
> 
> The series is organised as:
> 
> - patches 1-14 add the device tree bindings, the Metanoia vendor prefix,
>   the RISC-V board schema and the SoC block compatibles
> - patch 15 adds ARCH_METANOIA and selects the AX45MP errata
> - patches 16-23 add the reset, SPI, watchdog, MMC, PHY and USB changes
>   needed to build and probe on this SoC
> - patch 24 adds the MT2824 SoC and MT5824 EVB device trees
> - patch 25 adds the MAINTAINERS entry
> 
> The ATCSPI200 driver gains optional interrupt support for PIO transfers:
> when the controller IRQ is wired, the FIFOs and the end of transfer
> are serviced from the handler, with a fallback to polling when no IRQ
> is available.
> 
> The DWC MSHC controller on the evaluation board is wired to either an
> SD slot or an eMMC through a board jumper that the SoC cannot read. In
> the absence of a fixed card type in the device tree, the driver probes
> the eMMC first at 1.8 V and falls back to the SD slot at 3.3 V. The
> controller also needs custom tuning and HS400 PHY DLL handling, which
> is why it has its own sdhci_ops.
> 
> The MT2824 SoC contains other controllers not yet exposed (I2C, GPIO,
> pinctrl, Ethernet, DSP, ...). This first series allows accessing the
> evaluation board via its serial console, and all its storage options
> (SPI-NOR, eMMC, SD card). The watchdog and the USB port are also
> available.
> 
> The driver changes do not depend on the DTS at build time and are gated
> on the new compatible strings. For merge ordering, the DTS depends on the
> ARCH_METANOIA Kconfig entry (patch 15) and on the binding compatibles
> being accepted. The patches can therefore go through their respective
> subsystem trees, with the Kconfig, DTS and MAINTAINERS patches going
> through the RISC-V tree once the driver and binding patches have landed.

I kinda pointed it out elsewhere, but that's not actually the path for
the Kconfig, dts and MAINTAINERS bits. They go via the soc tree, after
being applied by a metanoia specific maintainer.

> 
> The series is based on v7.4-rc1.
> 
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
> Benoît Monin (25):
>       dt-bindings: vendor-prefixes: add Metanoia Communications
>       dt-bindings: riscv: add Metanoia SoC-based boards
>       dt-bindings: reset: add Metanoia MT2824
>       dt-bindings: power: reset: add Metanoia MT2824 reboot
>       dt-bindings: phy: add Metanoia USB2 PHY
>       dt-bindings: cache: andestech,ax45mp-cache: add MT2824 compatible
>       dt-bindings: interrupt-controller: sifive,plic-1.0.0: add Metanoia MT2824
>       dt-bindings: interrupt-controller: andestech,plicsw: add Metanoia MT2824
>       dt-bindings: timer: andestech,plmt0: add Metanoia MT2824
>       dt-bindings: mmc: snps,dwcmshc-sdhci: add Metanoia MT2824
>       dt-bindings: spi: andestech,ae350-spi: make DMA and interrupts optional
>       dt-bindings: spi: andestech,ae350-spi: add Metanoia MT2824
>       dt-bindings: usb: dwc2: add Metanoia MT2824
>       dt-bindings: watchdog: andestech,ae350-wdt: add Metanoia MT2824

Other than the tag issues in most of these, riscv and dt wise this looks
mostly fine. The reset/reboot stuff and probably missing clock support
are the only real problems.

Probably, I would split this series up into multiple smaller
submissions. spi, mmc, phy, usb, watchdog at least should be their own
mini series. clock/reset should probably be another, presumably also
with the reboot thing. What's left (interrupts, timer, cache I think)
can stay part of the dts series and probably go through the soc tree
together. For interrupts and timer, the maintainers are usually not
super responsive in terms of binding only series which is why they may
go via soc.

Cheers,
Conor.

>       riscv: add ARCH_METANOIA Kconfig entry
>       reset: simple: add Metanoia MT2824 support
>       spi: atcspi200: add optional interrupt support
>       spi: atcspi200: allow building for Metanoia SoCs
>       watchdog: atcwdt200: allow building for Metanoia SoCs
>       mmc: sdhci-of-dwcmshc: add MT2824 support
>       mmc: sdhci-of-dwcmshc: add MT2824 tuning and HS400 support
>       phy: metanoia: add USB2 PHY driver
>       usb: dwc2: add support for Metanoia MT2824
>       riscv: add Metanoia MT2824 SoC and MT5824 EVB support
>       MAINTAINERS: add RISC-V Metanoia SoC support

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