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From: Igor Velkov <iav@iav.lv>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Enrique Hernández Bello <ehbello@gmail.com>,
	lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
	bhelgaas@google.com, robh@kernel.org, heiko@sntech.de,
	linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Igor Velkov <iav@iav.lv>
Subject: Re: [PATCH RFC 0/2] PCI: rockchip-host: Retry training and hot-reset a JMB585 on RK3399
Date: Fri, 06 Nov 2026 07:09:25 +0200	[thread overview]
Message-ID: <20261106-rockchip-pcie-ltssm-trace-1@iav.lv> (raw)
In-Reply-To: <20261030-rockchip-pcie-s2idle-a53-1@iav.lv>

Hi Shawn,

I traced the LTSSM on the Helios64 (RK3399 + JMB585, x2, 2.5 GT/s) by
polling PCIE_CLIENT_DEBUG_OUT_0 about every 2 us during link training
and the waits after it. This changes what the RFC said, so here are the
data and a question.

A failing link bring-up looks like this:

- the LTSSM reaches L0 as fast as in a good one;
- then it leaves L0 for Recovery (RcvrLock/RcvrCfg/Idle, about 5 us)
  every 199..204 us, for as long as I watch: 488 times per 100 ms;
- link_st in BASIC_STATUS1 becomes 3 only 15..47 ms after training
  starts, or not within 700 ms; the latter is the "link training gen1
  timeout" with LTSSM 0x10;
- the RC shows nothing: AER and the device status are clear, and a dump
  of the client, core management and root port config registers is
  identical to a good bring-up.

A good bring-up has no Recovery entry after L0. A config read on a bad
link gets no completion; that is the abort I reported. 200 us is the
optional Flow Control Update timeout, so I suspect that one side does
not see the DLLPs of the other.

The state survives Recovery but not Detect: a port re-init or a hot
reset is just one more bring-up, with the same odds. So the hot reset
of patch 2/2 does not cure anything, and the time the link takes to
return is not a reliable sign either.

Unbind/bind cycles with a bad bring-up (a cycle is one training plus
one hot reset):

  Helios64, JMB585, x2                     6 of 104
  same, PHY refclk 100 MHz from NPLL       4 of 33
  same, num-lanes = <1>                    0 of 104
  ROCK Pi 4A, WD SN770 NVMe, x4            0 of 100
  same, num-lanes = <2>                    0 of 100

So it takes both lanes and the JMB585.

Is anything like this known for the RK3399 with a two-lane endpoint,
for example lane-to-lane skew of the transmitter, or a PHY setting that
affects it? And is there a bit in DEBUG_OUT_0/1 that tells which side
directs the Recovery?

Both boards ran the same build: v7.3.1 with the Armbian patches and the
tracing. The Helios64 DT has no ep-gpios there, the ROCK Pi 4A DT has.

Thanks,
Igor

  reply	other threads:[~2026-11-06  5:10 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-24  1:02 Igor Velkov via B4 Relay
2026-10-24  1:02 ` [PATCH RFC 1/2] PCI: rockchip-host: Retry link training that times out Igor Velkov via B4 Relay
2026-10-24  1:02 ` [PATCH RFC 2/2] PCI: rockchip-host: Hot-reset the endpoint before using the link Igor Velkov via B4 Relay
2026-10-26  9:08 ` [PATCH RFC 0/2] PCI: rockchip-host: Retry training and hot-reset a JMB585 on RK3399 Shawn Lin
2026-10-26 18:28   ` Igor Velkov
2026-10-27  0:44     ` Shawn Lin
2026-10-27  1:15       ` Igor Velkov
2026-10-28 17:31       ` Enrique Hernández Bello
2026-10-30 21:30         ` Igor Velkov
2026-11-06  5:09           ` Igor Velkov [this message]
2026-11-07  2:35             ` Shawn Lin
2026-11-08 23:05               ` Igor Velkov
2026-11-09  2:06                 ` Shawn Lin

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