From: Vikram Singh <vikram.singh3@oss.qualcomm.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
"Liang, Kan" <kan.liang@linux.intel.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Atish Kumar Patra <atishp@rivosinc.com>,
Anup Patel <anup.patel@oss.qualcomm.com>,
Will Deacon <will@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Beeman Strong <beeman@rivosinc.com>
Cc: Vikram Singh <vikram.singh3@oss.qualcomm.com>,
Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Palmer Dabbelt <palmer@sifive.com>,
Conor Dooley <conor@kernel.org>,
devicetree@vger.kernel.org
Subject: [PATCH v4 1/7] perf: Increase the maximum number of branches remove_loops() can process.
Date: Fri, 6 Nov 2026 23:09:36 +0530 [thread overview]
Message-ID: <20261106173942.3175069-2-vikram.singh3@oss.qualcomm.com> (raw)
In-Reply-To: <20261106173942.3175069-1-vikram.singh3@oss.qualcomm.com>
RISCV CTR extension supports a maximum depth of 256 last branch records.
Currently remove_loops() can only process 127 entries at max. This leads
to samples with more than 127 entries being skipped. This change simply
updates the remove_loops() logic to be able to process 256 entries.
Co-developed-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Signed-off-by: Vikram Singh <vikram.singh3@oss.qualcomm.com>
---
tools/perf/util/machine.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c
index 0d2ebf6a84bc..7e884ab38c5e 100644
--- a/tools/perf/util/machine.c
+++ b/tools/perf/util/machine.c
@@ -2315,25 +2315,32 @@ static void save_iterations(struct iterations *iter,
iter->cycles += be[i].flags.cycles;
}
-#define CHASHSZ 127
-#define CHASHBITS 7
-#define NO_ENTRY 0xff
+#define CHASHBITS 8
+#define NO_ENTRY 0xffU
-#define PERF_MAX_BRANCH_DEPTH 127
+#define PERF_MAX_BRANCH_DEPTH 256
/* Remove loops. */
+/* Note: Last entry (i==ff) will never be checked against NO_ENTRY
+ * so it's safe to have an unsigned char array to process 256 entries
+ * without causing clash between last entry and NO_ENTRY value.
+ */
static int remove_loops(struct branch_entry *l, int nr,
struct iterations *iter)
{
int i, j, off;
- unsigned char chash[CHASHSZ];
+ unsigned char chash[PERF_MAX_BRANCH_DEPTH];
memset(chash, NO_ENTRY, sizeof(chash));
- BUG_ON(PERF_MAX_BRANCH_DEPTH > 255);
+ BUG_ON(PERF_MAX_BRANCH_DEPTH > 256);
for (i = 0; i < nr; i++) {
- int h = hash_64(l[i].from, CHASHBITS) % CHASHSZ;
+ /* Remainder division by PERF_MAX_BRANCH_DEPTH is not
+ * needed as hash_64 will anyway limit the hash
+ * to CHASHBITS
+ */
+ int h = hash_64(l[i].from, CHASHBITS);
/* no collision handling for now */
if (chash[h] == NO_ENTRY) {
--
2.43.0
next prev parent reply other threads:[~2026-11-06 17:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-06 17:39 [PATCH v4 0/7] riscv: pmu: Add support for Control Transfer Records Ext Vikram Singh
2026-11-06 17:39 ` Vikram Singh [this message]
2026-11-06 17:39 ` [PATCH v4 2/7] riscv: pmu: Add Control transfer records CSR definations Vikram Singh
2026-11-06 17:39 ` [PATCH v4 3/7] riscv: Add Control Transfer Records extension parsing Vikram Singh
2026-11-06 17:39 ` [PATCH v4 4/7] riscv: pmu: Add infrastructure for Control Transfer Record Vikram Singh
2026-11-06 17:39 ` [PATCH v4 5/7] riscv: pmu: Add driver for Control Transfer Records Ext Vikram Singh
2026-11-06 17:39 ` [PATCH v4 6/7] riscv: pmu: Integrate CTR Ext support in riscv_pmu_dev driver Vikram Singh
2026-11-06 17:39 ` [PATCH v4 7/7] dt-bindings: riscv: add Sxctr ISA extension description Vikram Singh
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