From: Vikram Singh <vikram.singh3@oss.qualcomm.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
"Liang, Kan" <kan.liang@linux.intel.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Atish Kumar Patra <atishp@rivosinc.com>,
Anup Patel <anup.patel@oss.qualcomm.com>,
Will Deacon <will@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Beeman Strong <beeman@rivosinc.com>
Cc: Vikram Singh <vikram.singh3@oss.qualcomm.com>,
Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Palmer Dabbelt <palmer@sifive.com>,
Conor Dooley <conor@kernel.org>,
devicetree@vger.kernel.org
Subject: [PATCH v4 7/7] dt-bindings: riscv: add Sxctr ISA extension description
Date: Fri, 6 Nov 2026 23:09:42 +0530 [thread overview]
Message-ID: <20261106173942.3175069-8-vikram.singh3@oss.qualcomm.com> (raw)
In-Reply-To: <20261106173942.3175069-1-vikram.singh3@oss.qualcomm.com>
Add the S[m|s]ctr ISA extension description.
Co-developed-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Signed-off-by: Vikram Singh <vikram.singh3@oss.qualcomm.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index c9dc5d80c0ea..c0dae4f536b9 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -181,6 +181,13 @@ properties:
changes to interrupts as frozen at commit ccbddab ("Merge pull
request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
+ - const: smctr
+ description: |
+ The standard Smctr supervisor-level extension for the machine mode
+ to enable recording limited branch history in a register-accessible
+ internal core storage as ratified at commit 9c87013 ("Merge pull
+ request #44 from riscv/issue-42-fix") of riscv-control-transfer-records.
+
- const: smmpm
description: |
The standard Smmpm extension for M-mode pointer masking as
@@ -226,6 +233,13 @@ properties:
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
ratified state.")
+ - const: ssctr
+ description: |
+ The standard Ssctr supervisor-level extension for recording limited
+ branch history in a register-accessible internal core storage as
+ ratified at commit 9c87013 ("Merge pull request #44 from
+ riscv/issue-42-fix") of riscv-control-transfer-records.
+
- const: ssnpm
description: |
The standard Ssnpm extension for next-mode pointer masking as
@@ -1120,6 +1134,21 @@ properties:
- const: zilsd
- const: zca
+ # Smctr depends on Sscsrind
+ - if:
+ contains:
+ const: smctr
+ then:
+ contains:
+ const: sscsrind
+ # Ssctr depends on Sscsrind
+ - if:
+ contains:
+ const: ssctr
+ then:
+ contains:
+ const: sscsrind
+
allOf:
# Zcf extension does not exist on rv64
- if:
--
2.43.0
prev parent reply other threads:[~2026-11-06 17:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-06 17:39 [PATCH v4 0/7] riscv: pmu: Add support for Control Transfer Records Ext Vikram Singh
2026-11-06 17:39 ` [PATCH v4 1/7] perf: Increase the maximum number of branches remove_loops() can process Vikram Singh
2026-11-06 17:39 ` [PATCH v4 2/7] riscv: pmu: Add Control transfer records CSR definations Vikram Singh
2026-11-06 17:39 ` [PATCH v4 3/7] riscv: Add Control Transfer Records extension parsing Vikram Singh
2026-11-06 17:39 ` [PATCH v4 4/7] riscv: pmu: Add infrastructure for Control Transfer Record Vikram Singh
2026-11-06 17:39 ` [PATCH v4 5/7] riscv: pmu: Add driver for Control Transfer Records Ext Vikram Singh
2026-11-06 17:39 ` [PATCH v4 6/7] riscv: pmu: Integrate CTR Ext support in riscv_pmu_dev driver Vikram Singh
2026-11-06 17:39 ` Vikram Singh [this message]
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