From: Vikram Singh <vikram.singh3@oss.qualcomm.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
"Liang, Kan" <kan.liang@linux.intel.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Atish Kumar Patra <atishp@rivosinc.com>,
Anup Patel <anup.patel@oss.qualcomm.com>,
Will Deacon <will@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Beeman Strong <beeman@rivosinc.com>
Cc: Vikram Singh <vikram.singh3@oss.qualcomm.com>,
Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Palmer Dabbelt <palmer@sifive.com>,
Conor Dooley <conor@kernel.org>,
devicetree@vger.kernel.org
Subject: [PATCH v4 4/7] riscv: pmu: Add infrastructure for Control Transfer Record
Date: Fri, 6 Nov 2026 23:09:39 +0530 [thread overview]
Message-ID: <20261106173942.3175069-5-vikram.singh3@oss.qualcomm.com> (raw)
In-Reply-To: <20261106173942.3175069-1-vikram.singh3@oss.qualcomm.com>
To support Control Transfer Records (CTR) extension, we need to extend the
riscv_pmu framework with some basic infrastructure for branch stack
sampling. Subsequent patches will use this to add support for CTR in the
riscv_pmu_dev driver.
With CTR, the branches are stored into a hardware FIFO, which will be
sampled by software when perf events overflow. A task may be
context-switched between overflows, and to avoid leaking samples we need
to clear the last task's records when a task is context-switched in.
To do this we will be using the pmu::sched_task() callback added in this
patch.
Co-developed-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Signed-off-by: Vikram Singh <vikram.singh3@oss.qualcomm.com>
---
drivers/perf/riscv_pmu.c | 19 +++++++++++++++++++
drivers/perf/riscv_pmu_legacy.c | 2 ++
drivers/perf/riscv_pmu_sbi.c | 17 +++++++++++++++++
include/linux/perf/riscv_pmu.h | 19 ++++++++++++++++++-
4 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c
index 092e6c92dc2d..a1ae490d94c9 100644
--- a/drivers/perf/riscv_pmu.c
+++ b/drivers/perf/riscv_pmu.c
@@ -122,6 +122,19 @@ u64 riscv_pmu_ctr_get_width_mask(struct perf_event *event)
return GENMASK_ULL(cwidth, 0);
}
+static void riscv_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, struct task_struct *task,
+ bool sched_in)
+{
+ struct riscv_pmu *pmu;
+
+ if (!pmu_ctx)
+ return;
+
+ pmu = to_riscv_pmu(pmu_ctx->pmu);
+ if (pmu->sched_task)
+ pmu->sched_task(pmu_ctx, task, sched_in);
+}
+
u64 riscv_pmu_event_update(struct perf_event *event)
{
struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
@@ -252,6 +265,8 @@ static int riscv_pmu_add(struct perf_event *event, int flags)
cpuc->events[idx] = event;
cpuc->n_events++;
hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+ if (rvpmu->ctr_add)
+ rvpmu->ctr_add(event, flags);
if (flags & PERF_EF_START)
riscv_pmu_start(event, PERF_EF_RELOAD);
@@ -273,6 +288,8 @@ static void riscv_pmu_del(struct perf_event *event, int flags)
if (rvpmu->ctr_stop)
rvpmu->ctr_stop(event, RISCV_PMU_STOP_FLAG_RESET);
cpuc->n_events--;
+ if (rvpmu->ctr_del)
+ rvpmu->ctr_del(event, flags);
if (rvpmu->ctr_clear_idx)
rvpmu->ctr_clear_idx(event);
perf_event_update_userpage(event);
@@ -385,6 +402,7 @@ struct riscv_pmu *riscv_pmu_alloc(void)
for_each_possible_cpu(cpuid) {
cpuc = per_cpu_ptr(pmu->hw_events, cpuid);
cpuc->n_events = 0;
+ cpuc->ctr_users = 0;
for (i = 0; i < RISCV_MAX_COUNTERS; i++)
cpuc->events[i] = NULL;
cpuc->snapshot_addr = NULL;
@@ -403,6 +421,7 @@ struct riscv_pmu *riscv_pmu_alloc(void)
.start = riscv_pmu_start,
.stop = riscv_pmu_stop,
.read = riscv_pmu_read,
+ .sched_task = riscv_pmu_sched_task,
};
return pmu;
diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c
index 4d6461d6a74f..097841bde9ef 100644
--- a/drivers/perf/riscv_pmu_legacy.c
+++ b/drivers/perf/riscv_pmu_legacy.c
@@ -114,6 +114,8 @@ static void pmu_legacy_init(struct riscv_pmu *pmu)
BIT(RISCV_PMU_LEGACY_INSTRET);
pmu->ctr_start = pmu_legacy_ctr_start;
pmu->ctr_stop = NULL;
+ pmu->ctr_add = NULL;
+ pmu->ctr_del = NULL;
pmu->event_map = pmu_legacy_event_map;
pmu->ctr_get_idx = pmu_legacy_ctr_get_idx;
pmu->ctr_get_width = pmu_legacy_ctr_get_width;
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 76a43259390d..400de6bed369 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -796,6 +796,14 @@ static void pmu_sbi_reset_scounteren(void *arg)
csr_read(CSR_SCOUNTEREN) & ~BIT(pmu_sbi_csr_index(event)));
}
+static void pmu_sbi_ctr_add(struct perf_event *event, int flags)
+{
+}
+
+static void pmu_sbi_ctr_del(struct perf_event *event, int flags)
+{
+}
+
static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival)
{
struct sbiret ret;
@@ -855,6 +863,12 @@ static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag)
}
}
+static void pmu_sbi_sched_task(struct perf_event_pmu_context *pmu_ctx, struct task_struct *task,
+ bool sched_in)
+{
+ /* Call CTR specific Sched hook. */
+}
+
static int pmu_sbi_find_num_ctrs(void)
{
struct sbiret ret;
@@ -1506,6 +1520,8 @@ static int pmu_sbi_device_probe(struct platform_device *pdev)
pmu->pmu.attr_groups = riscv_pmu_attr_groups;
pmu->pmu.parent = &pdev->dev;
pmu->cmask = cmask;
+ pmu->ctr_add = pmu_sbi_ctr_add;
+ pmu->ctr_del = pmu_sbi_ctr_del;
pmu->ctr_start = pmu_sbi_ctr_start;
pmu->ctr_stop = pmu_sbi_ctr_stop;
pmu->event_map = pmu_sbi_event_map;
@@ -1517,6 +1533,7 @@ static int pmu_sbi_device_probe(struct platform_device *pdev)
pmu->event_mapped = pmu_sbi_event_mapped;
pmu->event_unmapped = pmu_sbi_event_unmapped;
pmu->csr_index = pmu_sbi_csr_index;
+ pmu->sched_task = pmu_sbi_sched_task;
ret = riscv_pm_pmu_register(pmu);
if (ret)
diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h
index 08fdcf6baf4e..58bafa173868 100644
--- a/include/linux/perf/riscv_pmu.h
+++ b/include/linux/perf/riscv_pmu.h
@@ -30,6 +30,13 @@
struct sse_event;
+#define MAX_BRANCH_RECORDS 256
+
+struct branch_records {
+ struct perf_branch_stack branch_stack;
+ struct perf_branch_entry branch_entries[MAX_BRANCH_RECORDS];
+};
+
struct cpu_hw_events {
/* currently enabled events */
int n_events;
@@ -49,6 +56,11 @@ struct cpu_hw_events {
bool snapshot_set_done;
/* A shadow copy of the counter values to avoid clobbering during multiple SBI calls */
u64 snapshot_cval_shcopy[RISCV_MAX_COUNTERS];
+ /* Saved branch records. */
+ struct branch_records *branches;
+
+ /* Active events requesting branch records */
+ int ctr_users;
};
struct riscv_pmu {
@@ -65,6 +77,8 @@ struct riscv_pmu {
int (*ctr_get_idx)(struct perf_event *event);
int (*ctr_get_width)(int idx);
void (*ctr_clear_idx)(struct perf_event *event);
+ void (*ctr_add)(struct perf_event *event, int flags);
+ void (*ctr_del)(struct perf_event *event, int flags);
void (*ctr_start)(struct perf_event *event, u64 init_val);
void (*ctr_stop)(struct perf_event *event, unsigned long flag);
int (*event_map)(struct perf_event *event, u64 *config);
@@ -72,10 +86,13 @@ struct riscv_pmu {
void (*event_mapped)(struct perf_event *event, struct mm_struct *mm);
void (*event_unmapped)(struct perf_event *event, struct mm_struct *mm);
uint8_t (*csr_index)(struct perf_event *event);
-
+ void (*sched_task)(struct perf_event_pmu_context *ctx, struct task_struct *task,
+ bool sched_in);
struct cpu_hw_events __percpu *hw_events;
struct hlist_node node;
struct notifier_block riscv_pm_nb;
+
+ unsigned int ctr_depth;
};
#define to_riscv_pmu(p) (container_of(p, struct riscv_pmu, pmu))
--
2.43.0
next prev parent reply other threads:[~2026-11-06 17:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-06 17:39 [PATCH v4 0/7] riscv: pmu: Add support for Control Transfer Records Ext Vikram Singh
2026-11-06 17:39 ` [PATCH v4 1/7] perf: Increase the maximum number of branches remove_loops() can process Vikram Singh
2026-11-06 17:39 ` [PATCH v4 2/7] riscv: pmu: Add Control transfer records CSR definations Vikram Singh
2026-11-06 17:39 ` [PATCH v4 3/7] riscv: Add Control Transfer Records extension parsing Vikram Singh
2026-11-06 17:39 ` Vikram Singh [this message]
2026-11-06 17:39 ` [PATCH v4 5/7] riscv: pmu: Add driver for Control Transfer Records Ext Vikram Singh
2026-11-06 17:39 ` [PATCH v4 6/7] riscv: pmu: Integrate CTR Ext support in riscv_pmu_dev driver Vikram Singh
2026-11-06 17:39 ` [PATCH v4 7/7] dt-bindings: riscv: add Sxctr ISA extension description Vikram Singh
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