[PATCH 0/2] clk: qcom: ipq6018/ipq8074: keep port 5 on uniphy1 at SGMII rates

[PATCH 0/2] clk: qcom: ipq6018/ipq8074: keep port 5 on uniphy1 at SGMII rates

[André Valentin]

On IPQ6018 and IPQ8074, port 5 can be clocked from uniphy1. Its RX and TX
frequency tables offer uniphy1 only for uniphy1 at 312.5 MHz (2500BASE-X).
In SGMII uniphy1 runs at 125 MHz, and a 1G or 100M rate that reaches the
RCG then picks uniphy0, or stays on uniphy1 with the wrong divider. These
two patches add uniphy1 / 1 and uniphy1 / 5, which the port 6 tables of
gcc-ipq8074 already have for uniphy2.

This came out of a review of an OpenWrt fix for QCA8081 egress corruption
on port 5, where the port RCGs were left on the RX clock by the
bootloader [1]. In the sequence I can reproduce there, the rate change
stops at the divider and the RCG keeps its parent, so these entries are
not exercised. They matter wherever a 1G or 100M rate does reach the RCG.

Tested on IPQ6010 (MikroTik Chateau 5G R17 ax, QCA8081 on port 5) with
6.18.55 plus the OpenWrt patches: after link-ups at 2.5G, 1G and 100M both
port 5 RCGs stay on uniphy1 (CFG 0x300) and pass traffic at line rate,
without errors on the port. The IPQ8074 change is build-tested only.

[1] https://github.com/openwrt/openwrt/pull/24566

André Valentin (2):
  clk: qcom: gcc-ipq6018: keep port 5 on uniphy1 at SGMII rates
  clk: qcom: gcc-ipq8074: keep port 5 on uniphy1 at SGMII rates

 drivers/clk/qcom/gcc-ipq6018.c | 4 ++++
 drivers/clk/qcom/gcc-ipq8074.c | 4 ++++
 2 files changed, 8 insertions(+)


base-commit: fa4ad798f6f681031775266044ba1b0cf3c670bd
-- 
2.47.3

[PATCH 1/2] clk: qcom: gcc-ipq6018: keep port 5 on uniphy1 at SGMII rates

[André Valentin]

Port 5 can be clocked from uniphy1, which runs at 312.5 MHz with the
PHY in 2500BASE-X and at 125 MHz in SGMII. The port 5 RX and TX
frequency tables serve uniphy1 only at 312.5 MHz: 125 MHz lists
uniphy1 / 2.5 and then uniphy0 / 1, 25 MHz lists uniphy1 / 12.5 and
then uniphy0 / 5. __clk_rcg2_select_conf() takes the first config that
gives the rate exactly, so once uniphy1 runs at 125 MHz, a 1G or 100M
rate that reaches the RCG moves the port onto uniphy0 whenever uniphy0
runs at 125 MHz, and otherwise leaves it on uniphy1 at 50 MHz (1G) or
10 MHz (100M).

Add uniphy1 / 1 to the 125 MHz configs and uniphy1 / 5 to the 25 MHz
configs. They go after the existing uniphy1 entries, which serve uniphy1
at 312.5 MHz, so that 2500BASE-X keeps its divider, and before uniphy0.

gcc-ipq8074 does the same for port 6, whose tables list uniphy2 / 1 and
uniphy2 / 5.

Suggested-by: Julius Bairaktaris <julius@bairaktaris.de>
Signed-off-by: André Valentin <avalentin@marcant.net>
---
 drivers/clk/qcom/gcc-ipq6018.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index 6943dc51153..a86b52e4276 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -513,11 +513,13 @@ static struct clk_rcg2 apss_ahb_clk_src = {
 
 static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
 	C(P_UNIPHY1_RX, 12.5, 0, 0),
+	C(P_UNIPHY1_RX, 5, 0, 0),
 	C(P_UNIPHY0_RX, 5, 0, 0),
 };
 
 static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
 	C(P_UNIPHY1_RX, 2.5, 0, 0),
+	C(P_UNIPHY1_RX, 1, 0, 0),
 	C(P_UNIPHY0_RX, 1, 0, 0),
 };
 
@@ -568,11 +570,13 @@ static struct clk_rcg2 nss_port5_rx_clk_src = {
 
 static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
 	C(P_UNIPHY1_TX, 12.5, 0, 0),
+	C(P_UNIPHY1_TX, 5, 0, 0),
 	C(P_UNIPHY0_TX, 5, 0, 0),
 };
 
 static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
 	C(P_UNIPHY1_TX, 2.5, 0, 0),
+	C(P_UNIPHY1_TX, 1, 0, 0),
 	C(P_UNIPHY0_TX, 1, 0, 0),
 };
 
-- 
2.47.3

[PATCH 2/2] clk: qcom: gcc-ipq8074: keep port 5 on uniphy1 at SGMII rates

[André Valentin]

Port 5 can be clocked from uniphy1, which runs at 312.5 MHz with the
PHY in 2500BASE-X and at 125 MHz in SGMII. The port 5 RX and TX
frequency tables serve uniphy1 only at 312.5 MHz: 125 MHz lists
uniphy1 / 2.5 and then uniphy0 / 1, 25 MHz lists uniphy1 / 12.5 and
then uniphy0 / 5. __clk_rcg2_select_conf() takes the first config that
gives the rate exactly, so once uniphy1 runs at 125 MHz, a 1G or 100M
rate that reaches the RCG moves the port onto uniphy0 whenever uniphy0
runs at 125 MHz, and otherwise leaves it on uniphy1 at 50 MHz (1G) or
10 MHz (100M).

Add uniphy1 / 1 to the 125 MHz configs and uniphy1 / 5 to the 25 MHz
configs. They go after the existing uniphy1 entries, which serve uniphy1
at 312.5 MHz, so that 2500BASE-X keeps its divider, and before uniphy0.

The port 6 tables already list uniphy2 / 1 and uniphy2 / 5 next to
uniphy2 / 2.5 and uniphy2 / 12.5.

Suggested-by: Julius Bairaktaris <julius@bairaktaris.de>
Signed-off-by: André Valentin <avalentin@marcant.net>
---
 drivers/clk/qcom/gcc-ipq8074.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 1329ea28d70..fb172b9aec0 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -1679,11 +1679,13 @@ static struct clk_regmap_div nss_port4_tx_div_clk_src = {
 
 static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
 	C(P_UNIPHY1_RX, 12.5, 0, 0),
+	C(P_UNIPHY1_RX, 5, 0, 0),
 	C(P_UNIPHY0_RX, 5, 0, 0),
 };
 
 static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
 	C(P_UNIPHY1_RX, 2.5, 0, 0),
+	C(P_UNIPHY1_RX, 1, 0, 0),
 	C(P_UNIPHY0_RX, 1, 0, 0),
 };
 
@@ -1749,11 +1751,13 @@ static struct clk_regmap_div nss_port5_rx_div_clk_src = {
 
 static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
 	C(P_UNIPHY1_TX, 12.5, 0, 0),
+	C(P_UNIPHY1_TX, 5, 0, 0),
 	C(P_UNIPHY0_TX, 5, 0, 0),
 };
 
 static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
 	C(P_UNIPHY1_TX, 2.5, 0, 0),
+	C(P_UNIPHY1_TX, 1, 0, 0),
 	C(P_UNIPHY0_TX, 1, 0, 0),
 };
 
-- 
2.47.3