[PATCH 0/5] clk: stm32: Add the STM32MP2 SYSCFG LTDC pixel clock mux

[PATCH 0/5] clk: stm32: Add the STM32MP2 SYSCFG LTDC pixel clock mux

[Gabriel Fernandez]

On STM32MP23x and STM32MP25x, the LTDC pixel clock is selected in the
SYSCFG DISPLAYCLKCR register among the LTDC kernel clock (RGB output),
the LVDS PHY pixel clock (reset value) and the DSI PHY byte lane clock.
The SYSCFG node is already referenced as the LTDC "ref" clock, but no
driver registers this clock, so the RGB output can't be used.

This series adds a clock driver for this mux. It is based on the RFC
sent by Dario [1] and on the driver delivered in the ST downstream
kernel.

The SYSCFG node is bound to the STM32MP2 SYSCFG driver, which populates
its sub-nodes. So, instead of an auxiliary device, the mux is described
by a clock-controller sub-node of the SYSCFG node:
- the mux parents are taken from its "clocks" property, so the inputs
  which don't exist on a SoC (no LVDS/DSI on STM32MP231/233 and
  STM32MP251/253) are simply omitted,
- it uses "#clock-cells = <1>" with a onecell provider, so the other
  clock selections of the SYSCFG can be added later without changing
  the binding.

The SoC devicetrees now use the clock-controller sub-node as the LTDC
"ref" clock instead of the SYSCFG node. Since no driver ever registered
a clock on the SYSCFG node, there is no functional change for existing
devicetrees.

Changes compared to the RFC [1]:
- clock-controller sub-node populated by the SYSCFG driver instead of
  an auxiliary device (RFC patch 3/4 dropped)
- parents described by clocks/clock-names instead of global names
- onecell provider and dt-bindings header for the SYSCFG clocks
- SoC devicetrees updated, Engicam board patches dropped (see above)

[1] https://lore.kernel.org/all/20261028135915.2665857-1-dario.binacchi@amarulasolutions.com/

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
---
Gabriel Fernandez (5):
      dt-bindings: clock: Add STM32MP25 SYSCFG clock controller
      dt-bindings: arm: stm32: Add clock-controller sub-node to STM32MP2 SYSCFG
      clk: stm32: Add STM32MP25 SYSCFG clock driver
      arm64: dts: st: add LTDC pixel clock controller on stm32mp23
      arm64: dts: st: add LTDC pixel clock controller on stm32mp25

 .../bindings/arm/stm32/st,stm32-syscon.yaml        |   6 +
 .../bindings/clock/st,stm32mp25-syscfg-clk.yaml    |  61 ++++++++++
 arch/arm64/boot/dts/st/stm32mp231.dtsi             |   8 ++
 arch/arm64/boot/dts/st/stm32mp235.dtsi             |   8 +-
 arch/arm64/boot/dts/st/stm32mp251.dtsi             |   8 ++
 arch/arm64/boot/dts/st/stm32mp255.dtsi             |   8 +-
 drivers/clk/stm32/Kconfig                          |  11 ++
 drivers/clk/stm32/Makefile                         |   1 +
 drivers/clk/stm32/clk-stm32mp25-syscfg.c           | 134 +++++++++++++++++++++
 .../dt-bindings/clock/st,stm32mp25-syscfg-clk.h    |  12 ++
 10 files changed, 255 insertions(+), 2 deletions(-)
---
base-commit: 630059a5a632377b9b7b487baccde92b7ae1dd47
change-id: 20261103-ups_mp25_clk_syscfg-6a4224156431

Best regards,
-- 
Gabriel Fernandez <gabriel.fernandez@foss.st.com>

[PATCH 1/5] dt-bindings: clock: Add STM32MP25 SYSCFG clock controller

[Gabriel Fernandez]

The SYSCFG of the STM32MP23x and STM32MP25x SoCs selects the LTDC pixel
clock among the LTDC kernel clock, the LVDS PHY pixel clock and the DSI
PHY byte lane clock.

Add the binding for this clock controller, described as a
clock-controller sub-node of the SYSCFG node, along with the header
defining the identifiers of the provided clocks.

The inputs are listed in the "ltdc", "lvds", "dsi" order so that the
ones missing on a SoC (no LVDS nor DSI on STM32MP231/233 and
STM32MP251/253) can be omitted at the end of the list. "#clock-cells"
is 1 so that the other clocks of the SYSCFG can be added later without
changing the binding.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
---
 .../bindings/clock/st,stm32mp25-syscfg-clk.yaml    | 61 ++++++++++++++++++++++
 .../dt-bindings/clock/st,stm32mp25-syscfg-clk.h    | 12 +++++
 2 files changed, 73 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp25-syscfg-clk.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp25-syscfg-clk.yaml
new file mode 100644
index 000000000000..027d14f28b0c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st,stm32mp25-syscfg-clk.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/st,stm32mp25-syscfg-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32MP2 SYSCFG clock controller
+
+maintainers:
+  - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+
+description: |
+  The SYSCFG of the STM32MP23x and STM32MP25x SoCs provides clocks, described
+  by a clock controller sub-node of the SYSCFG node.
+
+  The provided clocks are identified by the macros defined in
+  include/dt-bindings/clock/st,stm32mp25-syscfg-clk.h:
+    - CK_SYSCFG_PIX_LTDC: LTDC pixel clock, selected in the DISPLAYCLKCR
+      register among the LTDC kernel clock, used by the RGB parallel output,
+      the LVDS PHY pixel clock and the DSI PHY byte lane clock.
+
+properties:
+  compatible:
+    const: st,stm32mp25-syscfg-clk
+
+  "#clock-cells":
+    const: 1
+
+  clocks:
+    minItems: 1
+    items:
+      - description: LTDC kernel clock
+      - description: LVDS PHY pixel clock
+      - description: DSI PHY byte lane clock
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: ltdc
+      - const: lvds
+      - const: dsi
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+
+    clock-controller {
+        compatible = "st,stm32mp25-syscfg-clk";
+        #clock-cells = <1>;
+        clocks = <&rcc CK_KER_LTDC>, <&lvds>, <&dsi>;
+        clock-names = "ltdc", "lvds", "dsi";
+    };
+...
diff --git a/include/dt-bindings/clock/st,stm32mp25-syscfg-clk.h b/include/dt-bindings/clock/st,stm32mp25-syscfg-clk.h
new file mode 100644
index 000000000000..74673942898c
--- /dev/null
+++ b/include/dt-bindings/clock/st,stm32mp25-syscfg-clk.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2026 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_ST_STM32MP25_SYSCFG_CLK_H_
+#define _DT_BINDINGS_CLOCK_ST_STM32MP25_SYSCFG_CLK_H_
+
+#define CK_SYSCFG_PIX_LTDC	0
+
+#endif /* _DT_BINDINGS_CLOCK_ST_STM32MP25_SYSCFG_CLK_H_ */

-- 
2.43.0

[PATCH 2/5] dt-bindings: arm: stm32: Add clock-controller sub-node to STM32MP2 SYSCFG

[Gabriel Fernandez]

The LTDC pixel clock multiplexer of the STM32MP23x and STM32MP25x
SYSCFG is described by a clock-controller sub-node of the SYSCFG node.

Add this sub-node to the SYSCFG binding. It is required on STM32MP23x
and STM32MP25x and not allowed on the other SoCs.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
---
 Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
index a559f8b03b84..38c844e8f19d 100644
--- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
@@ -45,6 +45,10 @@ properties:
   "#size-cells":
     const: 1
 
+  clock-controller:
+    type: object
+    $ref: /schemas/clock/st,stm32mp25-syscfg-clk.yaml#
+
 patternProperties:
   "^phy@2[48]00$":
     type: object
@@ -80,6 +84,7 @@ allOf:
         - "#address-cells"
         - "#clock-cells"
         - "#size-cells"
+        - clock-controller
         - phy@2400
         - phy@2800
     else:
@@ -87,6 +92,7 @@ allOf:
         '#address-cells': false
         '#clock-cells': false
         '#size-cells': false
+        clock-controller: false
         phy@2400: false
         phy@2800: false
 

-- 
2.43.0

[PATCH 3/5] clk: stm32: Add STM32MP25 SYSCFG clock driver

[Gabriel Fernandez]

On STM32MP23x and STM32MP25x, the LTDC pixel clock is selected in the
SYSCFG DISPLAYCLKCR register among the DSI PHY byte lane clock, the LVDS
PHY pixel clock (reset value) and the LTDC kernel clock, the latter
being the one needed by the RGB (DPI) output.

No driver registers this clock, so the selection can't be changed from
its reset value and a display connected to the LTDC RGB output can't
work.

Add a driver registering this clock as a mux. The SYSCFG node is bound
to the STM32MP2 SYSCFG driver, which populates its sub-nodes, so the
driver is probed from the "st,stm32mp25-syscfg-clk" clock-controller
sub-node and uses the regmap of the parent SYSCFG node. The mux parents
are taken from the "clocks" property of the sub-node, and the clock is
exposed through a onecell provider so that the other SYSCFG clocks can
be added later.

Co-developed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
---
 drivers/clk/stm32/Kconfig                |  11 +++
 drivers/clk/stm32/Makefile               |   1 +
 drivers/clk/stm32/clk-stm32mp25-syscfg.c | 134 +++++++++++++++++++++++++++++++
 3 files changed, 146 insertions(+)

diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig
index 5dbd75cde657..a298983f5511 100644
--- a/drivers/clk/stm32/Kconfig
+++ b/drivers/clk/stm32/Kconfig
@@ -39,5 +39,16 @@ config COMMON_CLK_STM32MP257
 	help
 	  Support for stm32mp25x SoC family clocks.
 
+config COMMON_CLK_STM32MP25_SYSCFG
+	tristate "Clock driver for stm32mp25x SYSCFG clocks"
+	depends on COMMON_CLK_STM32MP257
+	select MFD_SYSCON
+	default COMMON_CLK_STM32MP257
+	help
+	  Support for the clocks provided by the stm32mp25x SYSCFG, i.e.
+	  the LTDC pixel clock source selection between the LTDC kernel
+	  clock (RGB output), the LVDS PHY pixel clock and the DSI byte
+	  lane clock.
+
 endif
 
diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile
index e04727b59449..8088d172651f 100644
--- a/drivers/clk/stm32/Makefile
+++ b/drivers/clk/stm32/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_COMMON_CLK_STM32MP135)	+= clk-stm32mp13.o clk-stm32-core.o reset-st
 obj-$(CONFIG_COMMON_CLK_STM32MP157)	+= clk-stm32mp1.o reset-stm32.o
 obj-$(CONFIG_COMMON_CLK_STM32MP215)	+= clk-stm32mp21.o clk-stm32-core.o reset-stm32.o
 obj-$(CONFIG_COMMON_CLK_STM32MP257)	+= clk-stm32mp25.o clk-stm32-core.o reset-stm32.o
+obj-$(CONFIG_COMMON_CLK_STM32MP25_SYSCFG)	+= clk-stm32mp25-syscfg.o
diff --git a/drivers/clk/stm32/clk-stm32mp25-syscfg.c b/drivers/clk/stm32/clk-stm32mp25-syscfg.c
new file mode 100644
index 000000000000..69b9a7592838
--- /dev/null
+++ b/drivers/clk/stm32/clk-stm32mp25-syscfg.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/st,stm32mp25-syscfg-clk.h>
+
+#define SYSCFG_DISPLAYCLKCR		0x5000
+#define DISPLAYCLKCR_DPIVSLVDS		GENMASK(1, 0)
+
+#define STM32MP25_SYSCFG_NUM_CLKS	(CK_SYSCFG_PIX_LTDC + 1)
+
+/*
+ * The LTDC pixel clock source is selected in SYSCFG_DISPLAYCLKCR among
+ * the DSI byte lane clock, the LVDS PHY pixel clock (reset value) and
+ * the LTDC kernel clock, which is used with the RGB (DPI) output.
+ *
+ * The parents are listed in the DPIVSLVDS field order, while .index refers
+ * to the "clocks" property of the node, ordered "ltdc", "lvds", "dsi" so
+ * that the inputs missing on a SoC can be omitted at the end of the list.
+ */
+static const struct clk_parent_data clk_pix_ltdc_parents[] = {
+	{ .index = 2 },	/* dsi */
+	{ .index = 1 },	/* lvds */
+	{ .index = 0 },	/* ltdc */
+};
+
+struct stm32mp25_syscfg_mux {
+	struct clk_hw hw;
+	struct regmap *regmap;
+};
+
+static inline struct stm32mp25_syscfg_mux *to_syscfg_mux(struct clk_hw *hw)
+{
+	return container_of(hw, struct stm32mp25_syscfg_mux, hw);
+}
+
+static u8 stm32mp25_syscfg_mux_get_parent(struct clk_hw *hw)
+{
+	struct stm32mp25_syscfg_mux *mux = to_syscfg_mux(hw);
+	unsigned int val;
+
+	regmap_read(mux->regmap, SYSCFG_DISPLAYCLKCR, &val);
+
+	return FIELD_GET(DISPLAYCLKCR_DPIVSLVDS, val);
+}
+
+static int stm32mp25_syscfg_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct stm32mp25_syscfg_mux *mux = to_syscfg_mux(hw);
+
+	return regmap_update_bits(mux->regmap, SYSCFG_DISPLAYCLKCR,
+				  DISPLAYCLKCR_DPIVSLVDS,
+				  FIELD_PREP(DISPLAYCLKCR_DPIVSLVDS, index));
+}
+
+static const struct clk_ops stm32mp25_syscfg_mux_ops = {
+	.get_parent = stm32mp25_syscfg_mux_get_parent,
+	.set_parent = stm32mp25_syscfg_mux_set_parent,
+	.determine_rate = clk_hw_determine_rate_no_reparent,
+};
+
+static int stm32mp25_syscfg_clk_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct clk_hw_onecell_data *clk_data;
+	struct clk_init_data init = { };
+	struct stm32mp25_syscfg_mux *mux;
+	int ret;
+
+	clk_data = devm_kzalloc_flex(dev, *clk_data, hws,
+				     STM32MP25_SYSCFG_NUM_CLKS);
+	if (!clk_data)
+		return -ENOMEM;
+
+	clk_data->num = STM32MP25_SYSCFG_NUM_CLKS;
+
+	mux = devm_kzalloc_obj(dev, *mux);
+	if (!mux)
+		return -ENOMEM;
+
+	/* The mux is a sub-node of the SYSCFG, whose regmap it shares */
+	mux->regmap = syscon_node_to_regmap(dev->parent->of_node);
+	if (IS_ERR(mux->regmap))
+		return dev_err_probe(dev, PTR_ERR(mux->regmap),
+				     "failed to get the SYSCFG regmap\n");
+
+	init.name = "clk_pix_ltdc";
+	init.ops = &stm32mp25_syscfg_mux_ops;
+	init.parent_data = clk_pix_ltdc_parents;
+	init.num_parents = ARRAY_SIZE(clk_pix_ltdc_parents);
+	init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
+	mux->hw.init = &init;
+
+	ret = devm_clk_hw_register(dev, &mux->hw);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to register %s\n",
+				     init.name);
+
+	clk_data->hws[CK_SYSCFG_PIX_LTDC] = &mux->hw;
+
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
+}
+
+static const struct of_device_id stm32mp25_syscfg_clk_of_match[] = {
+	{ .compatible = "st,stm32mp25-syscfg-clk" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, stm32mp25_syscfg_clk_of_match);
+
+static struct platform_driver stm32mp25_syscfg_clk_driver = {
+	.probe = stm32mp25_syscfg_clk_probe,
+	.driver = {
+		.name = "stm32mp25-syscfg-clk",
+		.of_match_table = stm32mp25_syscfg_clk_of_match,
+	},
+};
+module_platform_driver(stm32mp25_syscfg_clk_driver);
+
+MODULE_AUTHOR("Gabriel Fernandez <gabriel.fernandez@foss.st.com>");
+MODULE_DESCRIPTION("STM32MP25 SYSCFG clock driver");
+MODULE_LICENSE("GPL");

-- 
2.43.0

[PATCH 4/5] arm64: dts: st: add LTDC pixel clock controller on stm32mp23

[Gabriel Fernandez]

Describe the LTDC pixel clock multiplexer of the SYSCFG as a
clock-controller sub-node and use it as the LTDC "ref" clock instead of
the SYSCFG node itself.

Only the LTDC kernel clock is available as parent on STM32MP231; the
LVDS and DSI clocks are added on STM32MP235.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
---
 arch/arm64/boot/dts/st/stm32mp231.dtsi | 8 ++++++++
 arch/arm64/boot/dts/st/stm32mp235.dtsi | 8 +++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi
index fefbf6f4f153..6b6b4aa2bb5d 100644
--- a/arch/arm64/boot/dts/st/stm32mp231.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi
@@ -4,6 +4,7 @@
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+#include <dt-bindings/clock/st,stm32mp25-syscfg-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/regulator/st,stm32mp25-regulator.h>
 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
@@ -1125,6 +1126,13 @@ syscfg: syscon@44230000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			syscfg_clk: clock-controller {
+				compatible = "st,stm32mp25-syscfg-clk";
+				#clock-cells = <1>;
+				clocks = <&rcc CK_KER_LTDC>;
+				clock-names = "ltdc";
+			};
+
 			usb2_phy1: phy@2400 {
 				compatible = "st,stm32mp25-usb2phy1";
 				reg = <0x2400 0x24>;
diff --git a/arch/arm64/boot/dts/st/stm32mp235.dtsi b/arch/arm64/boot/dts/st/stm32mp235.dtsi
index 7a87c344a4fe..0ef5f2cdd18e 100644
--- a/arch/arm64/boot/dts/st/stm32mp235.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp235.dtsi
@@ -7,10 +7,16 @@
 
 &ltdc {
 	compatible = "st,stm32mp255-ltdc";
-	clocks = <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>;
+	clocks = <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>,
+		 <&syscfg_clk CK_SYSCFG_PIX_LTDC>, <&lvds>;
 	clock-names = "lcd", "bus", "ref", "lvds";
 };
 
+&syscfg_clk {
+	clocks = <&rcc CK_KER_LTDC>, <&lvds>, <&clk_dsi_txbyte>;
+	clock-names = "ltdc", "lvds", "dsi";
+};
+
 &rifsc {
 	lvds: lvds@48060000 {
 		compatible = "st,stm32mp255-lvds", "st,stm32mp25-lvds";

-- 
2.43.0

[PATCH 5/5] arm64: dts: st: add LTDC pixel clock controller on stm32mp25

[Gabriel Fernandez]

Describe the LTDC pixel clock multiplexer of the SYSCFG as a
clock-controller sub-node and use it as the LTDC "ref" clock instead of
the SYSCFG node itself.

Only the LTDC kernel clock is available as parent on STM32MP251; the
LVDS and DSI clocks are added on STM32MP255.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
---
 arch/arm64/boot/dts/st/stm32mp251.dtsi | 8 ++++++++
 arch/arm64/boot/dts/st/stm32mp255.dtsi | 8 +++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index dac3d2d23ff0..eec976e28dbd 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -4,6 +4,7 @@
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+#include <dt-bindings/clock/st,stm32mp25-syscfg-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
 #include <dt-bindings/regulator/st,stm32mp25-regulator.h>
@@ -2080,6 +2081,13 @@ syscfg: syscon@44230000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			syscfg_clk: clock-controller {
+				compatible = "st,stm32mp25-syscfg-clk";
+				#clock-cells = <1>;
+				clocks = <&rcc CK_KER_LTDC>;
+				clock-names = "ltdc";
+			};
+
 			usb2_phy1: phy@2400 {
 				compatible = "st,stm32mp25-usb2phy1";
 				reg = <0x2400 0x24>;
diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi
index 7a598f53a2a0..08cbc383af20 100644
--- a/arch/arm64/boot/dts/st/stm32mp255.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi
@@ -7,10 +7,16 @@
 
 &ltdc {
 	compatible = "st,stm32mp255-ltdc";
-	clocks = <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>;
+	clocks = <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>,
+		 <&syscfg_clk CK_SYSCFG_PIX_LTDC>, <&lvds>;
 	clock-names = "lcd", "bus", "ref", "lvds";
 };
 
+&syscfg_clk {
+	clocks = <&rcc CK_KER_LTDC>, <&lvds>, <&clk_dsi_txbyte>;
+	clock-names = "ltdc", "lvds", "dsi";
+};
+
 &rifsc {
 	lvds: lvds@48060000 {
 		compatible = "st,stm32mp255-lvds", "st,stm32mp25-lvds";

-- 
2.43.0

Re: [PATCH 2/5] dt-bindings: arm: stm32: Add clock-controller sub-node to STM32MP2 SYSCFG

[Conor Dooley]

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On Tue, Nov 10, 2026 at 11:42:17AM +0100, Gabriel Fernandez wrote:
> The LTDC pixel clock multiplexer of the STM32MP23x and STM32MP25x
> SYSCFG is described by a clock-controller sub-node of the SYSCFG node.
> 
> Add this sub-node to the SYSCFG binding. It is required on STM32MP23x
> and STM32MP25x and not allowed on the other SoCs.
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

Why does this need a child node at all, can't the clock controller
properties go straight into this syscon node?

Cheers,
Conor.

> ---
>  Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
> index a559f8b03b84..38c844e8f19d 100644
> --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
> +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
> @@ -45,6 +45,10 @@ properties:
>    "#size-cells":
>      const: 1
>  
> +  clock-controller:
> +    type: object
> +    $ref: /schemas/clock/st,stm32mp25-syscfg-clk.yaml#
> +
>  patternProperties:
>    "^phy@2[48]00$":
>      type: object
> @@ -80,6 +84,7 @@ allOf:
>          - "#address-cells"
>          - "#clock-cells"
>          - "#size-cells"
> +        - clock-controller
>          - phy@2400
>          - phy@2800
>      else:
> @@ -87,6 +92,7 @@ allOf:
>          '#address-cells': false
>          '#clock-cells': false
>          '#size-cells': false
> +        clock-controller: false
>          phy@2400: false
>          phy@2800: false
>  
> 
> -- 
> 2.43.0
> 

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